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Silicon Processing for the VLSI Era, Vol. 4: Deep-Submicron Process Technology (Repost)

Posted By: Specialselection
Silicon Processing for the VLSI Era, Vol. 4: Deep-Submicron Process Technology (Repost)

Stanley Wolf, "Silicon Processing for the VLSI Era, Vol. 4: Deep-Submicron Process Technology"
English | 2002-05 | ISBN: 096167217X | 423 pages | PDF | 79.9 mb

This well written reference book is highly recommended to anyone interested in the technology used to manufacture deep-submicron MOSFETs, i.e., MOSFETs requiring lithography in the 1/4 to 1/8-micron range. The first chapter nicely identifies several practical problems that appeared during the evolution of the MOSFET to ULSI, and the remainder of the book discusses processing solutions to those problems.
Major processing topics include thin gate oxides, self-aligned silicides, high- and low-k dielectrics, double and triple level metal interconnects, dual damascene copper interconnects, copper seed and electroplating technology, deep uv photoresists and tools, chemical-mechanical planarization, and processing issues unique to 300-mm wafers. State of the art CMOS topics including super-steep retrograde channel doping, punchthrough-control implants, source/drain engineering, shallow trench isolation, and more are used to illustrate the integration of deep-submicron processes into manufacturing. Increasing use of Si-Ge heterojunction bipolar transistors and silicon-on-insulator is anticipated and discussed.