Vsd - Physical Design Webinar Using Eda Tool 'Proton'

I call this 'freedom of EDA tools'

What you'll learn
Build, Verify and PNR any design, for which you have an RTL
Characterize any post-layout design in terms of frequency, net count, instance count, runtime and many more
Do entire floorplanning of chip online using steps mentioned in webinar
Requirements
You should have completed Physical design course on Udemy
You should have completed STA-1 course on Udemy
Description
Be it in any field - Change is inevitable. Let’s change the way we used to do Physical design. This time, no need to install tools on laptop, no licenses needed, no hidden costs, just your gmail login id and you are ready to design your first chip online. Find it hard to believe? 
I welcome you to my first “Physical Design” Webinar that happened on 20th Jan 2018 at 9am IST. This is 3-hour action-packed webinar with myself being the host and below 3 people from industry
Rajeev Srivastava -

Rajeev is technical advisor to webchip and also was one of the
developers of Proton while at Silverline Inc. Currently he is a Sr
Principal Physical Design Engineer at NXP.  While at Silverline, he was a
expert user of Proton and has worked with customers to use proton
successfully on many chip design projects. He will be helping with the
webinar today and show how to run the tools and also answer proton
related questions.


Aditya Pratap -
Aditya is the main developer and chief architect of Webchip.He was
also one of the main developers of open source EDA tool proton that we
will see in action today in our webinar.

Sanjeev Gupta -
Sanjeev is an VLSI & System design expert and also chief of operations at webchip.


Finally one word - 'LIVE' - pin placement, verification and routing
on WEB. All with zero license fee using industry grade EDA tool. That's
innovation. This is something which has never happened before.

Learn from the best, and expect a shift in your professional thinking.

I will see you all in webinar and happy learning



Overview

Section 1: Introduction

Lecture 1 Introduction

Section 2: 'Proton' features and capabilities

Lecture 2 Introduction to webchip.in

Lecture 3 Launch EDA tool 'Proton' LIVE on web

Section 3: RTL Design functionality verification and view physical cells

Lecture 4 Multiplier functionality description

Lecture 5 Functionality verification using iverilog on 'Proton'

Lecture 6 Import physical cells and view LEF

Lecture 7 LIVE Q&A with participants regarding LEF

Section 4: RTL Synthesis steps and Q&A

Lecture 8 Synthesis using 'qflow yosys'

Lecture 9 LIVE QnA with participants regarding synthesis algorithm

Lecture 10 Pre-layout timing analysis and LIVE QnA

Section 5: Floorplanning and power planning strategies

Lecture 11 Floorplanning concept and demonstration

Lecture 12 Detail discussion on power and gnd rails location

Lecture 13 LIVE QnA with participants regarding power planning

Section 6: Placement and Routing steps using 'Proton'

Lecture 14 Cell and automated pin placement concept and demo using graywolf

Lecture 15 LIVE QnA with participants regarding cell and pin placement

Lecture 16 Analyze placement and clock tree synthesis & demo flylines

Lecture 17 More LIVE QnA on flylines and demo routing step

Lecture 18 Commands to analyze and report routing statistics

Section 7: Post layout STA and future work

Lecture 19 Post layout timing analysis steps and discussion on new feature enablement

Lecture 20 LIVE QnA discussion with participants regarding timing ECO

Lecture 21 Assignment details and upcoming webinars announcement

Lecture 22 Plan going further and future tentative tool enhancements

Section 8: Conclusion

Lecture 23 Conclusion

Anyone who wants to learn chip designing using industry grade EDA tool,Anyone who has the limitation of tool installation and wants to design chip online