Cadence Virtuoso, Release Version IC6.1.8 ISR26 | 11.6 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled Virtuoso, Release Version IC6.1.8 ISR26 is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean layout of ICs and packages from a single schematic.
CCRs Fixed in IC6.1.8 and/or ICADVM20.1 ISR26 - Date: July 2022
2662741 Simulation stays in pending state when using the calcValForRel expression in the reliability setup
2661865 Delta marker label cannot be moved in IC6.1.8 and ICADVM20.1 ISR25
2661646 Incorrect calculation of maximum eye height and maximum eye width
2658601 Connectivity extractor for bundle nets with repeated bits not working as expected
2658158 Cannot initialize SRR license
2657538 Performance degradation in LSCS mode when RDBSynchronous is set to Full
2657528 Schematic behavior has been changed for multi-bit wire names in IC6.1.8 ISR25
2656127 Routability check reports incorrect spacing violation message for a short between pin and shape with different connectivity
2655960 LSCS has requirements for additional slots in session class for third-party simulator
2654780 Error when viewing or highlighting the violations of Checks/Asserts
2650842 Performance degradation in LSCS mode when RDBSynchronous is set to Full
2650571 Die export returns dbConcatTransform error when using the area transfer file option
2650526 Incorrect GDS file created during XStream Out translation with many vertices in IC6.1.8 and ICADVM20.1 ISR24
2649981 Routability check is not reporting pin access issues accurately
2649976 Routability check reports false spacing violations
2649138 Virtuoso Space-based Router reports a warning for missing route elements in the ctuRoute function
2649106 XStream Out creates a corrupt GDS file in IC6.1.8 and ICADVM20.1 ISR24
2647505 Virtuoso exits unexpectedly when you run вЂunlock all’ for the colors
2645779 Area estimator reports inaccurate area as it prefers signal nets during merging
2644604 HighCurrent design intent push-up from lower level fails when the top-level net is internal
2644577 Virtuoso stops responding when running a Monte Carlo simulation
2644274 Reliability analysis gets enabled automatically when the EMIR Analysis Setup form is opened
2644239 Virtuoso Visualization and Analysis XL exits unexpectedly when loading a .grf file with PSF selected as results database
2644210 Ensure that the calcVal upfront error check considers the run plan correctly
2643854 Incorrect tooltip on the Fault Level field in the Fault Rules form
2643798 Virtuoso exits unexpectedly due to segmentation faults in dalAliasMap::setDataChangeStatus
2643501 LibImport should ignore the technology file attachment of a pre-existing library and reassign the technology file to itself
2643177 Virtuoso exits unexpectedly when plotting AMS results during simulation
2642784 Oblong-shaped IOs have wrong orientation when exported to Clarity 3D Solver
2642587 Stretch command moves pathSeg outside a design partition
2642351 Diffstbprobe OCEAN script is not netlisted correctly and causes a simulation error (SPECTRE-16850)
2642347 SDR cannot start a stranded wire from another stranded group of wires
2642330 Virtuoso exits unexpectedly when using the Stranded Wire command in SDR
2641800 Change in design message should be displayed in the customer environment
2641318 Stranded Wire does not drop vias on pin when Current Estimation Mode is 'Nearest Island Current'
2639786 axlExportOutputView does not return the Checks/Asserts results on the first call
2639191 Signal Type should be set as value of reference view when executing Update Pins From View
2638963 Power router creates an empty fig group if power stripe or via creation fails
2638895 The form that defines the layer width/spacing constraints should be closed along with Pin Accessibility Checker form
2638825 Quantus av_extracted view missing multi-cell placed device properties
2636502 Multiple pop-ups block the screen when an EMIR simulation is run
2635968 Post-processing of the Checks/Asserts violations returns errors
2635921 XStream Out translation results in a large number of polygons and the DRC test shows non-orientable polygons errors
2635537 Issue in pg_function extraction if _vpmEnableBaseSupTracingThruShort is set
2634615 Either output expressions or MATLAB scripts return error in the Results view
2633495 Virtuoso RF Solution-Layout Versus Schematic Driven Flow: Issue with LVS database reader
2632751 Halo difference between IC6.1.8 ISR17 and IC6.1.8 ISR18
2632185 The termMapping CDF property of the ibit symbol in analoglib is set to an incorrect value
2631591 Virtuoso VDR menus do not end with ellipsis
2631586 Creating a wire using the default color option does not reflect the mask number correctly
2630886 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2630480 Cannot create ports for all components in a design
2630439 Selecting 'Show selected Cells' removes already selected boundary cells
2630364 Vias placed on shield are not aligned and causes cross topology
2629961 Edges of row in chopped rowRegion are not aligned with ndiff/pdiff WSPs
2629776 Layer sets handled incorrectly if the same path is specified multiple times in setup.loc
2629092 When creating a new layout with auto routed nets with shields, shield nets are not routed
2629068 Allegro Import and Allegro Export roundtrip scrambles orientation of oblong-shaped die IOs
2628824 Fault dropping flow does not work when using layout-based fault generation
2628733 Lock Unselected Vias is not respected correctly in ICADVM20.1 ISR24
2627984 The CAS tab in Annotation Browser does not display all results
2627763 Virtuoso exits unexpectedly during automatic shielding creation
2627625 Pre-run script ignores parameterization in ADE Assembler
2627324 The is_unconnected attribute extraction must be enhanced
2627298 Virtuoso Power Manager should only add the is_isolated attribute when all the connected nodes are already connected to isolation cells
2626414 Unable to generate an ADE netlist in the first attempt; works fine on recreating it
2625740 Device M5 is not running TRP with pdk2trp selection
2625470 Unable to launch Virtuoso when virtuoso201.conf.lock exists in $HOME/.cadence
2625116 Plotting dB20 in Virtuoso Visualization and Analysis XL and from the Direct Plot form creates different axes and units
2623708 Include molding compound definition in Virtuoso RF Solution and Clarity 3D Solver cross-fabric flow
2620957 Cannot sweep the value of a device parameter in a pre-run script
2619960 The Virtuoso Schematic Editor L license is not checked in when a text view is closed
2619409 Row snapping for multiple heights snaps devices outside rows
2619036 Virtuoso stops unexpectedly while loading history
2616530 Unable to exit Virtuoso in nograph mode due to corrupt lock files
2616521 Differences in routing when the pre-routes are part of the route when compared to the case when pre-routes are not part of the route
2616066 The spectre.opts tranFilterExtreme variable has no effect on the GUI in ADE Explorer
2614969 In ICADVM20.1 ISR23, ASIC(MST) fails to route mustJoin pins in a single row
2613222 Outputs with MATLAB scripts return errors when simulating multiple corners
2612730 Checks/Asserts results are not displayed when a simulation is run on cloud
2611868 Virtuoso Power Manager is unable to resolve pg_function and issues the LP-3082 warning
2611218 Allow running stb analysis with transient analysis for AMS without the need to enable ac analysis
2611122 Unexpected cyclic dependency detected when a global variable disabled for the test causes this dependency
2609614 The Voltus-Fi result database gets prefilled instead of the emir0_bin file
2608278 Virtuoso SystemVerilog Netlister is netlisting concatenated bus port connections incorrectly
2606229 DEF In translation does not map some vias to standard vias
2606214 MATLAB output expressions fails to evaluate for all corners
2604655 Asymmetric capacitor extracted in a fully symmetric structure
2602732 Virtuoso becomes unresponsive when running commands related to a constraint view
2599759 Incorrect temperature values when using a different variable name than temp
2596137 Iterated instances with modgenUseIteratedAsMfactor==t can result in non-synchronized GPE text pattern symbols and layout views
2595164 A device parameter expected to use a design variable uses a global variable instead
2586084 Generate All From Source should not create level1 design intent constraints if a layout master for an instance exists
2580925 Weird units are displayed in the Highlight legend for Self-Heating Effect
2579964 Abstract step does not create pins from all labels if textDisplays are present
2578528 Allow local variables to overwrite global variables when used in conditional statements
2573381 Variable dependency is lost in the netlist when the variable expression uses sqrt
2571549 Performance issue with a large number of model files due to a time-consuming call to the _axlGetDDSPFFilesInModelFiles function
2565603 Virtuoso Schematics XL license should not be checked out when working in Virtuoso Schematics L with a schematic view that contains design intent
2554348 Allegro Export must check that the view type is set to layout before exporting to Allegro
2553495 Unable to create statistical corners when the Save Simulation Data and Save Netlists options are deselected
2545473 Selecting Extend Fill on the Fill tab of the Auto P&R assistant results in the fill area extending beyond the row region
2542152 AutoCopyCellviewVars not honored if the test is associated with a config view
2535317 VAR() in the Temperature row of reliability analysis in not working as expected
2525044 Method to reset the spacing value using Constraint Editor should be simplified
2523773 Filter ignored in the maeExportOutputView command for the second test
2519581 Unable to set different values for the bandwidth parameter through design variable
2509056 AMS UNL netlisting fails intermittently when using VAR syntax to define an argument for the xrun command line
2502058 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2501660 Plotting results in Virtuoso Visualization and Analysis XL is taking much longer than expected
2497872 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2496772 Net capacitance for some nets is not displayed in Capacitance results view
2321187 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2309400 Failed to dump WSP using the wspDumpToFile function
2284554 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2278051 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2010461 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
1942685 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
1562579 setup.loc mechanism incorrectly creates duplicates of layer sets
1491057 Support parameterization with a pre-run script
1394928 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
1320420 Cannot sweep the value of a device parameter in a pre-run script
1271751 Layer sets handled incorrectly if duplicate paths are specified in setup.loc
1248065 Layer sets appear twice in the Layer Set Manager if layer set files are saved in ~/.cadence directory
1046032 Swept parameters are not passed to the pre-run script
1042229 In ADE XL, instance parameterization is not supported in the OCEAN pre-run script
910654 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
July 2022
2661865 Delta marker label cannot be moved in IC6.1.8 and ICADVM20.1 ISR25
2661646 Incorrect calculation of maximum eye height and maximum eye width
2658601 Connectivity extractor for bundle nets with repeated bits not working as expected
2658158 Cannot initialize SRR license
2657538 Performance degradation in LSCS mode when RDBSynchronous is set to Full
2657528 Schematic behavior has been changed for multi-bit wire names in IC6.1.8 ISR25
2656127 Routability check reports incorrect spacing violation message for a short between pin and shape with different connectivity
2655960 LSCS has requirements for additional slots in session class for third-party simulator
2654780 Error when viewing or highlighting the violations of Checks/Asserts
2650842 Performance degradation in LSCS mode when RDBSynchronous is set to Full
2650571 Die export returns dbConcatTransform error when using the area transfer file option
2650526 Incorrect GDS file created during XStream Out translation with many vertices in IC6.1.8 and ICADVM20.1 ISR24
2649981 Routability check is not reporting pin access issues accurately
2649976 Routability check reports false spacing violations
2649138 Virtuoso Space-based Router reports a warning for missing route elements in the ctuRoute function
2649106 XStream Out creates a corrupt GDS file in IC6.1.8 and ICADVM20.1 ISR24
2647505 Virtuoso exits unexpectedly when you run вЂunlock all’ for the colors
2645779 Area estimator reports inaccurate area as it prefers signal nets during merging
2644604 HighCurrent design intent push-up from lower level fails when the top-level net is internal
2644577 Virtuoso stops responding when running a Monte Carlo simulation
2644274 Reliability analysis gets enabled automatically when the EMIR Analysis Setup form is opened
2644239 Virtuoso Visualization and Analysis XL exits unexpectedly when loading a .grf file with PSF selected as results database
2644210 Ensure that the calcVal upfront error check considers the run plan correctly
2643854 Incorrect tooltip on the Fault Level field in the Fault Rules form
2643798 Virtuoso exits unexpectedly due to segmentation faults in dalAliasMap::setDataChangeStatus
2643501 LibImport should ignore the technology file attachment of a pre-existing library and reassign the technology file to itself
2643177 Virtuoso exits unexpectedly when plotting AMS results during simulation
2642784 Oblong-shaped IOs have wrong orientation when exported to Clarity 3D Solver
2642587 Stretch command moves pathSeg outside a design partition
2642351 Diffstbprobe OCEAN script is not netlisted correctly and causes a simulation error (SPECTRE-16850)
2642347 SDR cannot start a stranded wire from another stranded group of wires
2642330 Virtuoso exits unexpectedly when using the Stranded Wire command in SDR
2641800 Change in design message should be displayed in the customer environment
2641318 Stranded Wire does not drop vias on pin when Current Estimation Mode is 'Nearest Island Current'
2639786 axlExportOutputView does not return the Checks/Asserts results on the first call
2639191 Signal Type should be set as value of reference view when executing Update Pins From View
2638963 Power router creates an empty fig group if power stripe or via creation fails
2638895 The form that defines the layer width/spacing constraints should be closed along with Pin Accessibility Checker form
2638825 Quantus av_extracted view missing multi-cell placed device properties
2636502 Multiple pop-ups block the screen when an EMIR simulation is run
2635968 Post-processing of the Checks/Asserts violations returns errors
2635921 XStream Out translation results in a large number of polygons and the DRC test shows non-orientable polygons errors
2635537 Issue in pg_function extraction if _vpmEnableBaseSupTracingThruShort is set
2634615 Either output expressions or MATLAB scripts return error in the Results view
2633495 Virtuoso RF Solution-Layout Versus Schematic Driven Flow: Issue with LVS database reader
2632751 Halo difference between IC6.1.8 ISR17 and IC6.1.8 ISR18
2632185 The termMapping CDF property of the ibit symbol in analoglib is set to an incorrect value
2631591 Virtuoso VDR menus do not end with ellipsis
2631586 Creating a wire using the default color option does not reflect the mask number correctly
2630886 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2630480 Cannot create ports for all components in a design
2630439 Selecting 'Show selected Cells' removes already selected boundary cells
2630364 Vias placed on shield are not aligned and causes cross topology
2629961 Edges of row in chopped rowRegion are not aligned with ndiff/pdiff WSPs
2629776 Layer sets handled incorrectly if the same path is specified multiple times in setup.loc
2629092 When creating a new layout with auto routed nets with shields, shield nets are not routed
2629068 Allegro Import and Allegro Export roundtrip scrambles orientation of oblong-shaped die IOs
2628824 Fault dropping flow does not work when using layout-based fault generation
2628733 Lock Unselected Vias is not respected correctly in ICADVM20.1 ISR24
2627984 The CAS tab in Annotation Browser does not display all results
2627763 Virtuoso exits unexpectedly during automatic shielding creation
2627625 Pre-run script ignores parameterization in ADE Assembler
2627324 The is_unconnected attribute extraction must be enhanced
2627298 Virtuoso Power Manager should only add the is_isolated attribute when all the connected nodes are already connected to isolation cells
2626414 Unable to generate an ADE netlist in the first attempt; works fine on recreating it
2625740 Device M5 is not running TRP with pdk2trp selection
2625470 Unable to launch Virtuoso when virtuoso201.conf.lock exists in $HOME/.cadence
2625116 Plotting dB20 in Virtuoso Visualization and Analysis XL and from the Direct Plot form creates different axes and units
2623708 Include molding compound definition in Virtuoso RF Solution and Clarity 3D Solver cross-fabric flow
2620957 Cannot sweep the value of a device parameter in a pre-run script
2619960 The Virtuoso Schematic Editor L license is not checked in when a text view is closed
2619409 Row snapping for multiple heights snaps devices outside rows
2619036 Virtuoso stops unexpectedly while loading history
2616530 Unable to exit Virtuoso in nograph mode due to corrupt lock files
2616521 Differences in routing when the pre-routes are part of the route when compared to the case when pre-routes are not part of the route
2616066 The spectre.opts tranFilterExtreme variable has no effect on the GUI in ADE Explorer
2614969 In ICADVM20.1 ISR23, ASIC(MST) fails to route mustJoin pins in a single row
2613222 Outputs with MATLAB scripts return errors when simulating multiple corners
2612730 Checks/Asserts results are not displayed when a simulation is run on cloud
2611868 Virtuoso Power Manager is unable to resolve pg_function and issues the LP-3082 warning
2611218 Allow running stb analysis with transient analysis for AMS without the need to enable ac analysis
2611122 Unexpected cyclic dependency detected when a global variable disabled for the test causes this dependency
2609614 The Voltus-Fi result database gets prefilled instead of the emir0_bin file
2608278 Virtuoso SystemVerilog Netlister is netlisting concatenated bus port connections incorrectly
2606229 DEF In translation does not map some vias to standard vias
2606214 MATLAB output expressions fails to evaluate for all corners
2604655 Asymmetric capacitor extracted in a fully symmetric structure
2602732 Virtuoso becomes unresponsive when running commands related to a constraint view
2599759 Incorrect temperature values when using a different variable name than temp
2596137 Iterated instances with modgenUseIteratedAsMfactor==t can result in non-synchronized GPE text pattern symbols and layout views
2595164 A device parameter expected to use a design variable uses a global variable instead
2586084 Generate All From Source should not create level1 design intent constraints if a layout master for an instance exists
2580925 Weird units are displayed in the Highlight legend for Self-Heating Effect
2579964 Abstract step does not create pins from all labels if textDisplays are present
2578528 Allow local variables to overwrite global variables when used in conditional statements
2573381 Variable dependency is lost in the netlist when the variable expression uses sqrt
2571549 Performance issue with a large number of model files due to a time-consuming call to the _axlGetDDSPFFilesInModelFiles function
2565603 Virtuoso Schematics XL license should not be checked out when working in Virtuoso Schematics L with a schematic view that contains design intent
2554348 Allegro Export must check that the view type is set to layout before exporting to Allegro
2553495 Unable to create statistical corners when the Save Simulation Data and Save Netlists options are deselected
2545473 Selecting Extend Fill on the Fill tab of the Auto P&R assistant results in the fill area extending beyond the row region
2542152 AutoCopyCellviewVars not honored if the test is associated with a config view
2535317 VAR() in the Temperature row of reliability analysis in not working as expected
2525044 Method to reset the spacing value using Constraint Editor should be simplified
2523773 Filter ignored in the maeExportOutputView command for the second test
2519581 Unable to set different values for the bandwidth parameter through design variable
2509056 AMS UNL netlisting fails intermittently when using VAR syntax to define an argument for the xrun command line
2502058 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2501660 Plotting results in Virtuoso Visualization and Analysis XL is taking much longer than expected
2497872 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2496772 Net capacitance for some nets is not displayed in Capacitance results view
2321187 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2309400 Failed to dump WSP using the wspDumpToFile function
2284554 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2278051 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2010461 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
1942685 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
1562579 setup.loc mechanism incorrectly creates duplicates of layer sets
1491057 Support parameterization with a pre-run script
1394928 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
1320420 Cannot sweep the value of a device parameter in a pre-run script
1271751 Layer sets handled incorrectly if duplicate paths are specified in setup.loc
1248065 Layer sets appear twice in the Layer Set Manager if layer set files are saved in ~/.cadence directory
1046032 Swept parameters are not passed to the pre-run script
1042229 In ADE XL, instance parameterization is not supported in the OCEAN pre-run script
910654 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
July 2022
The Cadence Virtuoso System Design Platform links two world-class Cadence technologies—custom IC design and package/PCB design/analysis—creating a holistic methodology that automates and streamlines the design and verification flow for multi-die heterogeneous systems.
Leveraging the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment, it provides a single platform for IC-and package/system-level design capture, analysis, and verification. In addition, the Virtuoso System Design Platform provides an automated bidirectional interface with the Cadence SiP-level implementation environment and Clarity 3d Solver.
The Virtuoso System Design Platform allows IC designers to easily include system-level layout parasitics in the IC verification flow, enabling time savings by combining package/board layout connectivity data with the IC layout parasitic electrical model. The automatically generated “system-aware” schematic that results can then be easily used to create a testbench for final circuit-level simulation. The Virtuoso System Design Platform automates this entire flow, eliminating the highly manual and error-prone process of integrating system-level layout parasitic models back into the IC designer’s flow.
Cadence Virtuoso: Introduction
This video shows the basic introduction to one of the most used IC design tools in the industry and academia - Cadence virtuoso. It also shows how to edit schematic design in cadence virtuoso.
Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.
Product: Cadence Virtuoso
Version: IC6.1.8 ISR26 *
Supported Architectures: x86_64
Website Home Page : www.cadence.com
Languages Supported: english
System Requirements: Linux **
Size: 11.6 Gb
–––––––––––––––––––––––––––––––––––––
Standalone Software Shipped with IC6.1.8
–––––––––––––––––––––––––––––––––––––
Virtuoso Power System L……………………………(IC6.1.8)
Voltus-Fi Custom Power Integrity Solution XL…………(IC6.1.8)
Voltus-XFi Custom Power Integrity Solution…………..(IC6.1.8)
–––––––––––––––––––––––––––––––––––––
Cadence Product Releases Validated with IC6.1.8 ISR26
–––––––––––––––––––––––––––––––––––––
Allegro Sigrity…………………………………..(SIG 21.10.500)
Assura Physical Verification……………………….(ASSURA 04.16.111)
Conformal………………………………………..(CONFRML 21.20.100)
Extraction Tools (QRC/Quantus QRC)………………….(QUANTUS 20.12.000)
Innovus………………………………………….(INNOVUS 20.17.000)
Pegasus/Physical Verification System………………..(PEGASUS 21.31.000)
Physical Verification System……………………….(PVS 20.11.000)
Silicon-Package-Board Co-Design…………………….(SPB 17.20.082)
Spectre Circuit Simulators…………………………(SPECTRE 20.10.523)
XCELIUM(**)………………………………………(XCELIUMMAIN 22.03-s002, compatible from 22.03-s001)
………………………………………………..(XCELIUMMAIN 21.09-s009, compatible from 21.09-s003)
………………………………………………..(XCELIUMMAIN 21.03-s015, compatible from 21.03-s010)
………………………………………………..(XCELIUMMAIN 20.09-s022, compatible from 20.09-s001)
………………………………………………..(XCELIUMGREEN 22.03-v002, compatible from 22.03-v001)
………………………………………………..(XCELIUMAGILE 22.04-a001)
** The validated XCELIUM streams indicate the latest version used during
Virtuoso release testing. All XCELIUM streams are compatible starting with
the service packs listed in parentheses.
Standalone Software Shipped with IC6.1.8
–––––––––––––––––––––––––––––––––––––
Virtuoso Power System L……………………………(IC6.1.8)
Voltus-Fi Custom Power Integrity Solution XL…………(IC6.1.8)
Voltus-XFi Custom Power Integrity Solution…………..(IC6.1.8)
–––––––––––––––––––––––––––––––––––––
Cadence Product Releases Validated with IC6.1.8 ISR26
–––––––––––––––––––––––––––––––––––––
Allegro Sigrity…………………………………..(SIG 21.10.500)
Assura Physical Verification……………………….(ASSURA 04.16.111)
Conformal………………………………………..(CONFRML 21.20.100)
Extraction Tools (QRC/Quantus QRC)………………….(QUANTUS 20.12.000)
Innovus………………………………………….(INNOVUS 20.17.000)
Pegasus/Physical Verification System………………..(PEGASUS 21.31.000)
Physical Verification System……………………….(PVS 20.11.000)
Silicon-Package-Board Co-Design…………………….(SPB 17.20.082)
Spectre Circuit Simulators…………………………(SPECTRE 20.10.523)
XCELIUM(**)………………………………………(XCELIUMMAIN 22.03-s002, compatible from 22.03-s001)
………………………………………………..(XCELIUMMAIN 21.09-s009, compatible from 21.09-s003)
………………………………………………..(XCELIUMMAIN 21.03-s015, compatible from 21.03-s010)
………………………………………………..(XCELIUMMAIN 20.09-s022, compatible from 20.09-s001)
………………………………………………..(XCELIUMGREEN 22.03-v002, compatible from 22.03-v001)
………………………………………………..(XCELIUMAGILE 22.04-a001)
** The validated XCELIUM streams indicate the latest version used during
Virtuoso release testing. All XCELIUM streams are compatible starting with
the service packs listed in parentheses.
Supported Platforms and Operating Systems
Bitness of Operating System: x64
Architecture: x86_64
Supported OS: RHEL 6.5, RHEL 7, SLES 11, SLES 12
Bitness of Operating System: x64
Architecture: x86_64
Supported OS: RHEL 6.5, RHEL 7, SLES 11, SLES 12
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Added by 3% of the overall size of the archive of information for the restoration
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Added by 3% of the overall size of the archive of information for the restoration
No mirrors please