Mentor Graphics ModelSim 2020.4

Mentor, a Siemens business, is pleased to announce the availability of ModelSim 2020.4, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment.

Release Notes For ModelSim 2020.4 - Date: Oct 13 2020

SystemVerilog Defects Repaired in 2020.4
- QSIM-64132 - Vlog sometimes gave incorrect errors like:
- ** Error: while parsing file test.sv(50): Failed to find the name 'get_type' in scope 'tpkg'
- For names like 'pkg::typename::get_type() where "typename" is a typedef name resolving to a class.
- QSIM-64922 - Vlog reported the error:
- ** Error: test.sv(7) Illegal reference to an interface type C::Intf in implements clause.
- In cases where "C" was a parameterized class type and 'Intf" was a typedef name referenceing an interface class.
VHDL Defects Repaired in 2020.4
- QSIM-65962 - During compilation with the -autoorder and -quiet switches, if semantic errors were encountered during the refresh phase, the errors would not be printed. This behavior is incorrect, and now all errors are printed, though other compilation logging messages are suppressed.
- QSIM-66278 - Large data structures that take over 2Gbytes of space would crash if default initialization is used. For this to happen the default value for all fields in the data structure must be 0 or NULL. Explicitly initializing the object will work around the issue.
- QSIM-65639 - The design.bin could have incorrect bounds on signals. This occurs if the signal bounds depend on functions calls. An these functions use the std.textio.





Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.

ModelSim eases the process of finding design defects with an intelligently engineered debug environment.

The ModelSim HDL simulator provides FPGA customers with an easy and cost-effective way to speed up FPGA development and testing. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a higher quality FPGA design before entering the lab, allowing time spent in the lab to be more productive and focused.

In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.

The ModelSim debug environment efficiently displays design data for analysis and debug of all languages. ModelSim allows many debug and analysis capabilities to be employed post-simulation on saved results, as well as during live simulation runs.

ModelSim shares a common front end and user interface with Mentor's flagship simulator Questa. This allows customers to easily upgrade to Questa should they need higher performance and support for Advanced Verification capabilities.

Intro to Verilog and ModelSim, Part1


Intro to Verilog and ModelSim, Part2


Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world’s most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

Product: Mentor Graphics ModelSim
Version: 2020.4 *
Supported Architectures: 64bit / 32bit
Website Home Page : www.mentor.com
Language: english
System Requirements: PC / Linux **
Size: 4.9 Gb