Mentor Graphics Calibre 2014.4
Mentor Graphics Calibre 2014.4 | 1.8 Gb
Mentor Graphics, a technology leader in electronic design automation providing products, consulting services and award-winning support for the world's leading electronics and semiconductor companies, announced the new version Calibre 2014.4 - physical verification software as its tool of choice for complex deep-submicron IC designs.
Mentor's IC verification and sign-off includes not only traditional rule-based physical verification and parasitic extraction, but also new capabilities and automated technologies that help improve yield by enhancing the design itself.
Calibre is the overwhelming market share leader and the industry standard for IC physical verification, due to the outstanding performance, accuracy and reliability of Calibre products. Over the last two years, Calibre nmDRC has reduced average DRC runtime by a factor of five, while Calibre's innovative Hyperscaling and MTFlex technologies have cut memory requirements in half. Calibre nmDRC also reduced overall cycle time with incremental DRC, which allows designers to make DRC runs in parallel. As DRC violations are reported, designers can immediately fix and recheck just the affected areas, while the initial DRC run continues.
To handle complex and multi-variate, multi-dimensional checks that are not adequately addressed by traditional design rules, Calibre nmDRC's equation-based DRC (eqDRC) capability enables designers to express design rule checks as continuous, multi-dimensional functions that accurately and precisely reflect underlying physical interactions. With eqDRC, designers can use Calibre nmDRC to address complex DFM issues that other DRC tools simply can't handle.
Calibre nmLVS provides actual device geometry measurement, programmable electrical rule checking, and sophisticated interactive debugging capabilities to ensure accurate circuit verification and further improve the designer's productivity.
Physical Verification
- Calibre nmDRC: With the new GLOBALNETID function you can now identify hierarchical nets with DFM PROPERTY.
- Calibre Pattern Matching: Flexible Extent Patterns now allow you to specify a dynamic extent that reduces in size in conjunction with a constrained pattern edge.
- Calibre 3DSTACK: System Netlist Generator (SNG) can now easily create full device netlist for complex stacked systems and represent all source netlists for 3d assembly with multiple die.
Circuit Verification
- Calibre xACT: As technologies get smaller and smaller, xACT is improving memory performance to keep up with the increased amount of data generated by designs down to 10 nm.
- Calibre nmLVS: To make LVS easier for our customers who use LVS BOX, we have added the ability to define Black Box and Grey Box cells. As well, we can now define swappable pins for these blocks.
- Calibre PERC: To assist our customer with reducing the runtime of Calibre® PERC when millions of waivers are present, Mentor Graphics has dramatically improved the performance of waiver processing in 2014.4.
Interfaces
- Calibre DESIGNrev: ASCII RDB files containing polygons with more than 8192 vertices can now be read by DESIGNrev which will allow results from tools such as PERC LDL to be read.
- Calibre Interactive: A unique name is now used for the script created for each DRC HTML Report run making it easier to create different HTML reports.
- Calibre RealTime: Calibre RealTime will now output error and warning messages to the Cadence CIW window making those easier to view in the native environment.
- Calibre RVE: You can convert results from an ASCII format Calibre results database (RDB) to error markers and route guides in Synopsys IC Compiler which allows you to use familiar ICC tools for debug.
- Calibre nmDRC: With the new GLOBALNETID function you can now identify hierarchical nets with DFM PROPERTY.
- Calibre Pattern Matching: Flexible Extent Patterns now allow you to specify a dynamic extent that reduces in size in conjunction with a constrained pattern edge.
- Calibre 3DSTACK: System Netlist Generator (SNG) can now easily create full device netlist for complex stacked systems and represent all source netlists for 3d assembly with multiple die.
Circuit Verification
- Calibre xACT: As technologies get smaller and smaller, xACT is improving memory performance to keep up with the increased amount of data generated by designs down to 10 nm.
- Calibre nmLVS: To make LVS easier for our customers who use LVS BOX, we have added the ability to define Black Box and Grey Box cells. As well, we can now define swappable pins for these blocks.
- Calibre PERC: To assist our customer with reducing the runtime of Calibre® PERC when millions of waivers are present, Mentor Graphics has dramatically improved the performance of waiver processing in 2014.4.
Interfaces
- Calibre DESIGNrev: ASCII RDB files containing polygons with more than 8192 vertices can now be read by DESIGNrev which will allow results from tools such as PERC LDL to be read.
- Calibre Interactive: A unique name is now used for the script created for each DRC HTML Report run making it easier to create different HTML reports.
- Calibre RealTime: Calibre RealTime will now output error and warning messages to the Cadence CIW window making those easier to view in the native environment.
- Calibre RVE: You can convert results from an ASCII format Calibre results database (RDB) to error markers and route guides in Synopsys IC Compiler which allows you to use familiar ICC tools for debug.
Mentor Graphics Calibre 2014.4
About Mentor Graphics
Mentor Graphics is a technology leader in electronic design automation providing products, consulting services and award-winning support for the world's leading electronics and semiconductor companies. We offer the broadest portfolio of best-in-class hardware and software solutions focused on IC design, place & route, physical verification, functional verification, FPGA/PLD, design-for-test, PCB design and emerging technologies such as ESL. Innovative tools from Mentor Graphics solve demanding design challenges, including scalable solutions for functional verification; cutting-edge technology for place & route, design-for-manufacturability and mixed-level IC design verification; award-winning test compression technology; embedded software development systems; and market-leading integrated system design solutions.
Name: Mentor Graphics Calibre
Version: 2014.4 18.13
Home: www.mentor.com
Interface: english
OS: Linux 64bit
Size: 1.8 Gb
Mentor Graphics Calibre 2014.4
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