The Verilog Hardware Description Language, 5 Edition (repost)

The Verilog TM hardware description language is widely used in both industry and academia for the description of digital systems. The language supports the early conceptual stages of design with its behavioral level of abstraction and the later implementation stages with its structural level of abstraction.

The language provides hierarchical constructs, allowing the designer to control the complexity of description. The Verilog TM Hardware Description Language, 5 Edition takes a tutorial approach to presenting the language. It starts with a tutorial introduction which presents the major features of the language by example. It then continues with a more complete discussion of the language constructs. Numerous examples are provided to allow the reader to easily learn (and re-learn!) by example. Finally, a formal description of the language is provided in the Appendix. Overall, the presentation balances a learn-by-example style with a definitive discussion of the language.

The Verilog TM Hardware Description Language, Second Edition assumes a knowledge of introductory logic design and software programming. As such, the book is of use to practicing integrated circuit design engineers, and undergraduate and graduate electrical or computer engineering students. The tutorial introduction provides enough information for students in an introductory logic design course to make simple use of logic simulation as part of their laboratory experience. The rest of the book could then be used in upper level logic design and architecture courses. The Verilog TM Hardware Description Language, Second Edition is a valuable resource for engineers and students interested in modeling digital systems. Included in the book comes a disk that contains a DOS version of the VeriWellTM Verilog simulator as well as examples from the book. The examples can be simulated and modified and resimulated. The simulator can also be used to solve the exercises.