Digital Design With Systemverilog Hdl

Master SystemVerilog fundamentals with hands-on circuit design, taught by an engineer who understands beginner struggles

What you'll learn

Gain a solid understanding of HDL fundamentals using SystemVerilog.

Understand the ASIC and FPGA design flow from high-level architecture through RTL design and simulation with ModelSim.

Be able to write clean, synthesizable SystemVerilog code using dataflow, behavioral, and structural styles - and know when to use each

Learn how to design combinational and sequential logic circuits (MUX, Adders, Priority Encoder, ALU, Register, Counter, FSMs and single-port RAM memory).

Requirements

Motivation and curiosity to learn Digital Design!

Basic knowledge of digital logic components such as logic gates (AND, OR, NOT), truth tables, multiplexers, decoders, and simple sequential elements like flip-flops.

Some programming experience (e.g., C, C++, or Python) is helpful but not required, it will make it easier to adapt to the coding aspects of hardware description languages.

Description

Master SystemVerilog Fundamentals through Hands-On Circuit DesignAre you ready to take your first steps into the world of digital design and verification?This course gives you the practical skills and confidence to move from theory to working designs — all through SystemVerilog.We’ll start from the very basics and progress step by step, covering the essential building blocks of digital systems: multiplexers, encoders, ALUs, registers, finite state machines, and memory. Every topic includes clear explanations, practical coding examples, and simulation in ModelSim so you can see how theory transforms into working circuits.Unlike other courses, this one is hands-on and project-based. You won’t just watch code — you’ll write it, simulate it, and solve real problems, just like in the industry.By the end of this course, you will:Master HDL fundamentals: Learn the three main modeling styles — dataflow, behavioral, and structural.Write clean RTL code: Develop synthesizable SystemVerilog for real designs.Understand the design flow: From architecture to RTL and simulation.Design key digital circuits: Implement and verify MUXes, priority encoders, ALUs, registers, FSMs, and single-port RAM.Build confidence: Learn not just what to write, but how to think like a design/verification engineer.This course is perfect for:Students in Electrical and Computer Engineering who want to strengthen their HDL foundations.Beginners in digital design who want a guided, hands-on approach.Junior engineers preparing for technical interviews in VLSI, ASIC, or FPGA design.No prior experience in SystemVerilog is required. A basic understanding of logic gates and binary operations is enough — everything else is taught step by step.Join now, and let’s start building digital systems together!

Overview

Section 1: Introduction

Lecture 1 Welcome & Course Introduction

Lecture 2 Agenda

Lecture 3 Course Coverage & Learning Goals

Lecture 4 What is an HDL?

Lecture 5 SystemVerilog vs. Verilog

Lecture 6 ASIC vs. FPGA

Lecture 7 Digital Design Flow Overview

Lecture 8 Introduction to Verification

Section 2: Modelsim Simulator

Lecture 9 Agenda

Lecture 10 Installing ModelSim

Lecture 11 Running Your First Simulation “Hello World”

Lecture 12 Clarifications

Section 3: Multiplexers: Dataflow & Behavioral Design

Lecture 13 Agenda

Lecture 14 MUX Specification

Lecture 15 Designing a 2:1 MUX – Dataflow Style

Lecture 16 Designing a 4:1 MUX – Dataflow Style

Lecture 17 Designing a 2:1 MUX – Behavioral Style

Lecture 18 Designing a 4:1 MUX – Behavioral Style

Lecture 19 4:1 MUX Simulation

Lecture 20 Using "begin" and "end" in Code

Lecture 21 "assign" vs. "always_comb"

Lecture 22 Wire, Reg, and Logic in SystemVerilog

Section 4: Priority Encoder: Structural Design

Lecture 23 Agenda

Lecture 24 Designing a 4:1 MUX – Structural Style

Lecture 25 4-Bit Priority Encoder Explained

Lecture 26 16-Bit Priority Encoder Specification

Lecture 27 16-Bit Priority Encoder Architecture

Lecture 28 16-Bit Priority Encoder – Running an Example

Lecture 29 Designing 16-Bit Priority Encoder

Lecture 30 16-Bit Priority Encoder Simulation

Lecture 31 Assigment 3 Resourses

Section 5: Arithmetic Logic Unit (ALU)

Lecture 32 Agenda

Lecture 33 ALU Specification

Lecture 34 Working with Buses (Vectors)

Lecture 35 Bitwise Operators Explained

Lecture 36 Reduction Operators Explained

Lecture 37 Shift Operators Explained

Lecture 38 quality & Relational Operators Explained

Lecture 39 Designing the ALU

Lecture 40 ALU Simulation

Section 6: Registers & Counters

Lecture 41 Agenda

Lecture 42 Understanding Flip-Flops

Lecture 43 Register Basics

Lecture 44 Blocking vs. Non-Blocking Assignments (Part 1)

Lecture 45 Blocking vs. Non-Blocking Assignments (Part 2)

Lecture 46 8-Bit Register Specification

Lecture 47 Designing an 8-Bit Register

Lecture 48 8-Bit Register Simulation

Lecture 49 16-Bit Counter Specification

Lecture 50 16-Bit Counter Architecture

Lecture 51 Designing a 16-Bit Counter

Lecture 52 6-Bit Counter Simulation

Lecture 53 Enrichment on always blocks

Section 7: Finite State Machines (FSMs)

Lecture 54 Agenda

Lecture 55 What is a Finite State Machine?

Lecture 56 Mealy vs. Moore FSM Models

Lecture 57 1101 Sequence Detector Specification

Lecture 58 Mealy FSM – 1101 State Diagram

Lecture 59 Mealy FSM – Sequence Detector Design

Lecture 60 Mealy FSM Simulation

Lecture 61 Moore FSM – 1101 State Diagram

Lecture 62 Moore FSM – Sequence Detector Design

Lecture 63 Moore FSM Simulation

Lecture 64 Assigment 4 Resourses

Section 8: Memory Design

Lecture 65 Agenda

Lecture 66 What is a Memory?

Lecture 67 Types of Memory – ROM vs. RAM

Lecture 68 Memory vs. Registers

Lecture 69 Single-Port RAM Specification

Lecture 70 Designing a Single-Port RAM

Lecture 71 Single-Port RAM Simulation

Engineers looking to gain the basic skills needed for a job in Digital Design or Verification.,Students who want to master SstemVerilog HDL for projects and academic success.,Curious engineers from related fields who want to enrich their knowledge of hardware design.