Cadence XCELIUM 21.09.013 | 51.9 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, is pleased to announce the availability of XCELIUM 21.09.013 (XCELIUMMAIN) is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.
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AVSREQ-140392 ASSERTION_SVA $sampled in disable iff
AVSREQ-148672 PROFILER_MEM_XPROF xmsim crash while using -mem_xprof
AVSREQ-149670 XPROPAGATION_GENERAL cg crash when enabling xprop + enable_var_opt_core
AVSREQ-152734 CORE_RAND Recent librnc causing crash with customer scenario
AVSREQ-147920 SIM_PERFORMANCE xmelab *F,INTERR: INTERNAL EXCEPTION tl_elwait_count_expr - bad expr 850 VST_E_UNKNOWN
AVSREQ-151170 SIM_TCL deposit -scope does not return a correct execution status and does break the -execute in stop command
AVSREQ-130926 PROFILER_SIM_RUNTIME Another concern with PBSR and -profile
AVSREQ-92758 PARSE_SV xmvlog: *EXPRLC and EXPSMC with constructs using inside construct
AVSREQ-146222 ELAB_VHDL VHDL generic map from generic slice to default "others" not properly executed
AVSREQ-149015 ASSERTION_SIM assertoff does not accept ":" as scope name
AVSREQ-149584 COVERAGE_ALL_COVERAGES IMC is crashing when it is unable to load coverage database - sev 0 customer can't reproduce - Ext high
AVSREQ-143124 SV_INTERFACE XMELAB crash pointing to Message cu_vifc_find_master_always
AVSREQ-143462 LP_1801 Support key: for isolation_power_net in query_isolation
AVSREQ-115609 VHDL_PARSE xmvhdl_p generates large number of EXPEND error messages for an extra "," in port map of VHDL
AVSREQ-103591 SPECMAN_COV WARN_UNGRADABLE_ITEM using instance_ranges
AVSREQ-138150 SPECTRE_AMSD SOC level PA RTL AMS sims giving "unable to resolve power supply" error with DVS CM
AVSREQ-149618 RAND_SOLVER Solver using stale value generated by a function call inside constraint block
AVSREQ-107079 ASSERTION_SVF $past usage outside of assertion
AVSREQ-141056 JUPITER_BRIDGE High egress time in customer design when cells contains regs, and -xminitialize is used
AVSREQ-145617 GLS_GENERAL xmelab: *F,INTERR: INTERNAL EXCEPTION - cgtm_evalcc - missed the stream
AVSREQ-100644 DMS_ELAB Signal which has no driver is toggling in AMS simulations
AVSREQ-135711 SIM_PERFORMANCE assignments to vector variable split across generate scopes does not keep correct values
AVSREQ-141738 ASSERTION_SVA xmsim: *E,ASRTST: Assertion failure ($sampled in disable iff)
AVSREQ-148321 PARSE_SV Wrong SVRFDR error when using Resolution Function.
AVSREQ-133339 DMS_AXUM Issue with probe to analog content with SystemVerilog bind to SPICE in Mixed Signal Simulation
AVSREQ-147191 JUPITER_BRIDGE runtime assertion in src/simulator/recipe_execution.inl:2912
AVSREQ-136681 GLS_SDF GLS simulation with SDF of interconnect delay behavior abnormal
AVSREQ-130296 SIMVISION_GENERAL 'Load Signal' waveform option fails when group name has a square bracket
AVSREQ-136932 SIM_SV memory load of a slice with a default value doesnt work
AVSREQ-119271 ASSERTION_SIM Simulation taking huge time with large number of range in SVA assertion
AVSREQ-146780 COVERAGE_FUNCTIONAL $signed in coverpoint is blowing up bin count.
AVSREQ-127428 SV_DPI Issue with compiled cpp on CentOS7
AVSREQ-149528 SIM_PERFORMANCE Verilog memory write data corrupted with -enable_nba_opt perf option
AVSREQ-150437 SIM_TCL [Xcelium] "release" doesn't work with "force -release 50ns object_name = value" setting.
AVSREQ-152046 LP_TCL Values of the keys - isolation_power_net/isolation_ground_net of query_isolation command is incorrect
AVSREQ-146162 SV_CLASSES xmsim crash for function call in constraints
AVSREQ-151371 ELAB_SV During elaboration, xmelab INTERR (vxt_subvst default 652)
AVSREQ-138661 SPECMAN_COV using per_instance in cover group affects item gradeability
AVSREQ-147241 PARSE_SV XCELIUM xmdc INTERNAL EXCEPTION
AVSREQ-148101 ELAB_SV Elaboration crash due to UVM code - xcu_docsp_uniquification - found duplicate class specs for class uvm_sequencer_param_base
AVSREQ-144540 SIM_SV_VHDL Not able to force VHDL port/signal from verilog variable. VHDL side remains U
AVSREQ-153060 ELAB_BIND Elaboration fails to resolve parameter from CU scope
AVSREQ-129662 SIM_SV after time reset, signal on language boundary is set to 'U'
AVSREQ-126255 XPROPAGATION_GENERAL X-Propagation Disabled for Procedures in VHDL
AVSREQ-146978 GLS_PERFORMANCE timing check violation only with "SHM_RESET_DEFAULTS 1"
AVSREQ-149406 RAND_GENERAL Modifying rand_mode on struct arrays has no effect in Xcelium constraint solver
AVSREQ-135499 SIM_CONGRUENCY Congruency support in Dual Snapshot ( MSIE )
AVSREQ-145150 SIMVISION_GENERAL Safety Debug View - multiple selections are confusing users
AVSREQ-103597 DMS_ELAB xmsim crash ssl_trdrv_valuep - odd method
AVSREQ-145782 LP_1801 Query commands execute twice instead of once.
AVSREQ-150599 GLS_GENERAL [Feature req.] Generate a list of signals when the wire leaves X if the time at X exceeds a certain length of time.
AVSREQ-144097 JUPITER_BRIDGE Improve naccing of instances inside compressor and decompressor in ATPG TB
AVSREQ-146993 DMS_SIM Simulation crash when using the stop -at_resfunc debug tcl command
AVSREQ-134870 DMS_LP_AMS LP MS CUNSIF soft error not generated for CM on power domain boundary
AVSREQ-149591 LP_1801 Improve performance of find_objects
AVSREQ-151698 LP_1801 Elaboration crash when using iso_hybrid option
AVSREQ-137393 SV_PARAMETERS xmelab crashed due to genvar variable name
AVSREQ-141036 ELAB_SV The xmelab warning 'BIGWBS' not showing correct instance
AVSREQ-141775 SIM_SV 32-bit simulator behaves differently compared to the 64-bit version
AVSREQ-145286 ELAB_CLONE Elaboration crash with xmclone flow and SystemC uncauterized
AVSREQ-134799 ASSERTION_SIM Simulation performance huge degradation with assertion
AVSREQ-145532 DMS_ELAB xmelab: *E,CUFGPM :: loop generate construct support in +force_ms
AVSREQ-149474 SPECMAN_E Load crash with numeric type field under sys
AVSREQ-143628 XPROPAGATION_GENERAL xprop disabled with localparam used for reset value
AVSREQ-135703 ELAB_SV_VHDL Allow binding to interface inside the bbconnect module
AVSREQ-143578 PARSE_SV SVFWET - unsupported forward declaration of enum type (-enable_fwd_enum and -enable_use_before_decl_in_class)
AVSREQ-151861 LP_1801 DUPGCN error happens in 21.06-a001
AVSREQ-148087 SIM_SV xmsim crash when using the SimVision Simulation Cycle Debugger.
AVSREQ-148819 FUNC_SAFETY_XFSG The equivalent fault is different in SA0 and SA1.
AVSREQ-149816 ELAB_PERF elab memory overhead when parameters are stored in pib
AVSREQ-139047 CORE_RAND Random checkers=2 causes internal errors
AVSREQ-157718 LP_1801 *E,DUPGCN: [LPS] PG pin (VDDC) of cell instance was previously connected to a supply net at this new connection request can not be established
AVSREQ-144984 PARSE_SV SVNT2S error with new -enable_wire_type_param option
AVSREQ-140224 MSIE_ELAB MESSAGE: sv_seghandler - trapno -1 addr((nil))
AVSREQ-145793 FUNC_SAFETY_CONCURRENT XCELIUM21.04_e139 crashed in Concurrent FI
AVSREQ-151643 XRUN_GENERAL Parallel makelib-endlib compile mode causing xrun tool crash:"exec_makelib_parallel_append_log cant open log file"
AVSREQ-152041 GLS_PERFORMANCE GLS simulations runtime performance issue
AVSREQ-141778 SIM_SV Unexpected behavior with "value -keys" tcl command
AVSREQ-132974 GLS_PERFORMANCE xmelab -ntc_level 3 wallclock is 2.5x to 3x compared to without
AVSREQ-141027 PARSE_SV Xcelium always consider *.gz file is a zip file even it is normal .v file
AVSREQ-148389 MSIE_ELAB autohref generation flow misses some cross partition OOMR cases
AVSREQ-112201 PARSE_SV Please support `wrealXState and `wrealZState as legal values for System Verilog Parameters
AVSREQ-146748 FUNC_SAFETY_CONCURRENT CDN_FAULT_CLKTREE caused many "DD" faults to "DU"
AVSREQ-147540 LP_1801 Don't retain time variables
AVSREQ-138845 DMS_AXUM Cannot bind on spice using smos10hv technology : Recursive subcircuit call loop found
AVSREQ-150057 DMS_ELAB Elaboration crashed with -rnm_tech and -wreal wreal1driver
AVSREQ-108717 SIMVISION_DB_UTIL 2087010 CCR SimVision abort when trying to export
AVSREQ-93925 ASSERTION_SVA $sampled fails in disable iff clause of assertion
AVSREQ-150810 SV_PERFORMANCE verilog tasks cause poor performance than competitor
AVSREQ-123952 LP_1801 Inout type power port of PA model causes power net corruption
AVSREQ-147651 DEBUG_DESIGN_DATABASE Indago schematic fails to trace VHDL signal connection over multiple libraries
AVSREQ-110047 MSIE_SIMULATION Signal not driven correctly after deposit from the HDL
AVSREQ-144249 SV_PERFORMANCE newperf opt switch -enable_alcomb_sens_lsp_opt causes Specman DUT error
AVSREQ-132053 SV_PORTS SystemVerilog macro model issue (Logic to Real) in Xcelium
AVSREQ-153896 SIM_PERFORMANCE Using -lwd_complete resulting in core dump
AVSREQ-148138 PARSE_SV Simulation crashed after calling system task $stacktrace
AVSREQ-124288 LP_1801 location information of Isolation needed in "lps_verbose".
AVSREQ-125532 GLS_GENERAL Xcelium VPI Incorrect Value Returned Issue
AVSREQ-146771 XRUN_SYSC xmsc library not found when using -L./../.. notation
AVSREQ-142442 SPECMAN_COMPILE e file translation lingers
AVSREQ-145681 RAND_SOLVER New solver ignores condition in inline dist constraint
AVSREQ-147953 GLS_GENERAL MUX output is getting corrupted when both deposits around inputs to the MUX and the internal node of the mux cell are probed.
AVSREQ-138020 GLS_GENERAL Setup1 :: Elab crash when -afile is used
AVSREQ-148994 JUPITER_BRIDGE JUPITER | MSIE | Fix large time being taken in computing checksum for modules having large number of oomrs in MSIE mode
AVSREQ-121259 ASSERTION_SIM assignment of a property local variable fails
AVSREQ-147424 LP_1801 ISOCUNS Unsupported language construct detected for isolation
AVSREQ-137777 LP_1801 Convert xmlib2cdb execs to comply with all AVS tools
AVSREQ-121381 MSIE_ELAB DSSVAR Error in multi-xrun incremental elaboration
AVSREQ-145772 SIM_SV xmsim INTERR: sv_seghandler - trapno -1 addr(0x8cdbe3) Task run_phase (filee: file_name, line: line_no, in pkg_name)
AVSREQ-125106 SV_DYNAMIC_DATATYPES *E,WOUPXR An expression with queue datatype is not allowed
AVSREQ-144641 GLS_TIMING TC violation when -enable_ntc3_perf is added
AVSREQ-149485 COVERAGE_ALL_COVERAGES libucis core dump
AVSREQ-144061 SPECMAN_COV Coverage UCIS API: support for no_collect coveritems
AVSREQ-142574 VPI_GENERAL $writememh is currently not supported for ref ports
AVSREQ-145206 MSIE_ELAB Possible bug causing elaboration failure while analyzing MSIE partitioning with no error message
AVSREQ-133006 ELAB_PERF irun taking 6+ hours on ixcom generated snapshot for CPU design
AVSREQ-132983 GLS_GENERAL Elaboration Internal error
AVSREQ-91941 XPROPAGATION_GENERAL XPWDIS and XPATT message confusing to users
AVSREQ-141457 SIM_MLTYPEMAP mltypemap enhancement
AVSREQ-143701 LP_1801 Support for the key primary_power_net in query_isolation
AVSREQ-143705 LP_1801 Support for key retention_power_net in query_retention
AVSREQ-149828 CORE_SV_IN xmsim Internal Crash After Indago TCL Re-Elaboration
AVSREQ-141927 XRUN_GENERAL -gdbelab with -symbols use xmelab executable and not xmelab_sym
AVSREQ-123011 SYSC_GENERAL Inconsistent behavior with sc_buffer
AVSREQ-147394 LP_1801 Don't retain time, realtime, wreal, electrical, and string variables
AVSREQ-151753 ELAB_SV xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-115377 PARSE_SV NAMOOL error in Gate Level simulation
AVSREQ-148927 JUPITER_GLST XMSIM crashes after enabling waveform
AVSREQ-144281 LP_1801 Query should return full hierarchical path on isolation keys primary_power_net and isolation_power_net
AVSREQ-144908 SV_PARAMETERS Mixed signal simulation crashes with MESSAGE vst_is_forgen_parameter - unexpected vst kind 'VST_D_OOMR'
AVSREQ-147735 MSIE_ELAB generated externs.sv file name is getting cut-off after 64 chars
AVSREQ-100062 ASSERTION_SVA SVA: Unable to use $sampled in a disable iff clause
AVSREQ-156315 SPECMAN_DEBUG print_stack_trace() prints wrong stack
AVSREQ-148351 VPI_GENERAL NORELO error occurs when using uvm_hdl_release.
AVSREQ-121213 ASSERTION_SIM Assertion failure in simulation does not make sense
AVSREQ-133056 SV_GENERAL streaming operator - unpacking array of structs
AVSREQ-143465 LP_1801 Support for query_pg_info_cell
AVSREQ-153596 ELAB_SV INTERR: NO ERROR for error code 0
AVSREQ-146212 ASSERTION_SIM Getting False Assertion Failures
AVSREQ-147085 SV_GENERAL ILLFMT error when using %p insind $write
AVSREQ-121059 DBG_TRANSRECORD_SDI_VERILOG UVM transactions wrongly rendered in Simvision
AVSREQ-150540 RAND_GENERAL xmsim *F, INTERR with vst_get_source_marker() when using seed_trace
AVSREQ-149225 SIMVISION_MS Lost analog signals from Unified Database convert to vcd format
AVSREQ-120985 DMS_LICENSE The option licinfo doesn't provide DMSO root cause
AVSREQ-146820 SIM_SV Dumping memory in data only format
AVSREQ-152409 ELAB_CLONE Variable on LHS of always_ff not getting updated
AVSREQ-143467 LP_1801 Support for query_supply_net
AVSREQ-152216 DEBUG_DESIGN_DATABASE Indago loads files incorrectly for persistent_sources_debug switch and autofetch used together
AVSREQ-131268 LP_1801 User-defined states coverage defined in add_power_state
AVSREQ-143564 JUPITER_BRIDGE linker failed with error from "native_runtime.cpp" in DSS mode
AVSREQ-146584 ELAB_PERF Large elab times (12 hours) in non timing gate builds
AVSREQ-147235 COVERAGE_CODE Fatal internal error reported when expression coverage is enabled
AVSREQ-134819 ELAB_SV Xcelium 20.09 crashes, 20.03 hangs after elab and 18.09 runs fine with the same design database
AVSREQ-152212 DMS_ELAB INTERNAL Exception error while elaboration ::DR traverse too much times
AVSREQ-140536 LP_1801 [Implementation] Support hard macro - Phase 1
AVSREQ-99091 SV_GENERAL Cryptic UNSRFA compiler error when struct members selected in field automation macro
AVSREQ-138416 DMS_PERF Reduce time spent in vsto_is_constain_spice_oomr_ref
AVSREQ-142492 IP_PROTECT_GENERAL Encryption error 'DECERR'
AVSREQ-122990 XRUN_MULTI_CORE xrun continuing with xmsim despite failing xmelab/mcebuild
AVSREQ-142003 SIM_USABILITY E,NCMCMP in tb migration
AVSREQ-142917 SPECMAN_COMPILE Invalid pointer encountered by GC at load phase
AVSREQ-118260 ELAB_SV xmelab: *E,MULAXX : always_ff : Signal initialization in declaration considered as driver
AVSREQ-150211 RAND_DEBUG Need a way to display failing portion of constraint on SAT timeout
AVSREQ-144946 COVERAGE_GENERAL tool crash with 20.09.009 passes with 19.09.010
AVSREQ-140768 LP_1801 ASRTST error due to assertion control not applied
AVSREQ-144727 LP_1801 Feature Request to add support in xcelium to get ISO_INPUT & ISO_OUTPUT in a generic way
AVSREQ-147381 RAND_SOLVER F.INTERR: INTERNAL EXCEPTION in randomization
AVSREQ-150616 SIM_USABILITY No EndError tag is reported for error with option -enable_msg_marker on xrun: *E, VLGERR
AVSREQ-92962 SIM_SV Support for mailbox as a class type parameter
AVSREQ-148359 JUPITER_BRIDGE JUP_GL_EVAL : Elaboration crash as MCGFE failed in this ATPG case, degradation with Apr Agile release
AVSREQ-92720 SIM_SV Add support for mailbox as class type parameter
AVSREQ-109445 FUNC_SAFETY_SIM Incorrect fault injection time and saif recording time with checkpoints
AVSREQ-141337 LP_1801 Report unsupported UPF commands in a file
AVSREQ-85035 SIM_USABILITY xm_mirror slices of packed array
AVSREQ-102576 PROFILER_SIM_RUNTIME Support -profile argument with PBSR for core digital (and mixed signal) simulation
AVSREQ-152347 SIM_PERFORMANCE FATAL crash on elaboration vst_elem_datatype () - invalid class, class 748
AVSREQ-149085 PARSE_SV Xcelium crashed when invoking tcl stop command
AVSREQ-147751 LP_1801 *N,FOOESR, The find_objects command returns no objects
AVSREQ-144776 SIM_PERFORMANCE Simulation mismatch caused by gprune optimization
AVSREQ-139295 SIM_PERFORMANCE Cont assign case-1
AVSREQ-144105 FUNC_SAFETY_CONCURRENT Memory leakage w/ BADEL in XCELIUM21.01_e981_lnx86_GPLV3_N20210115143022211688
AVSREQ-144771 LP_1801 feedthrough wire is not propagating upf_always_on declared reg value
AVSREQ-149621 DEBUG_DESIGN_DATABASE xmelab with -createdebugdb/-lwdgen resulted in significant increase in size of LWD (3x normal snapshot)
AVSREQ-145297 ASSERTION_PERFORMANCE Slow performance on assertion -off -on
AVSREQ-147886 SV_PARAMETERS INTERR dt_get_known_datatype hit unknown datatype with local type param
AVSREQ-145825 ASSERTION_PERFORMANCE Xcelium get poor performance if there's until in assertion property
AVSREQ-148230 LP_1801 create a unique message when assertion in CAC does not exist
AVSREQ-146372 SIM_USABILITY E,NCMCST in TB migration
AVSREQ-150244 ELAB_SV xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-138458 ELAB_SV To change BNDWRN message for supported items
AVSREQ-92427 PARSE_SV ref event.triggered value is wrong
AVSREQ-138221 SV_DPI Support for longint one dimensional unpacked array type in DPI export function
AVSREQ-146277 SV_GENERAL xmsim crash ( MESSAGE: Anonymous continuous assignment )
AVSREQ-146506 XRUN_GENERAL xrun triggers MKLIBR tag when trying to create a directory
AVSREQ-149935 PARSE_SV Fatal error when enabling coverage
AVSREQ-122504 LP_1801 ERROR:The 'input' pin 'DFT_SPARE[2]' defined for cell 'x' in library 'xx' is either not defined or defined with different direction in the cell 'x' in library 'xxx'
AVSREQ-140975 SV_PERFORMANCE xmsim INTERR : Parallel block sub-process
AVSREQ-144151 JUPITER_GLST Build time degradation in customer design
AVSREQ-142364 LP_1801 [LPS: -lps_net_split] Why these samples are different?
AVSREQ-155251 DMS_LP_AMS INTERR at elab for LP setup
AVSREQ-143975 FUNC_SAFETY_HIER_EXPORT Wrong name extracted during design hierarchy extraction
AVSREQ-87626 PARSE_SV Request to make EXPRLC error a warning for easier migrations
AVSREQ-140219 ELAB_PERF Override parameter value at simulation time
AVSREQ-145195 MSIE_ELAB While doing primary elaboration we get xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-146595 SIM_SV xmelab pmp/dmp sanity failure with debug kit shared for AVSREQ-142277
AVSREQ-144784 SPECTRE_AMSD ams_flex PBSR cold restart failed with spectre terminated prematurely due to fatal error
AVSREQ-111427 SV_PERFORMANCE XMSIM : 2X CPU degradation with -memopt
AVSREQ-146413 SIM_SV Simulation got *F, INTERR if not use linedebug
AVSREQ-147950 XPROPAGATION_GENERAL misleading warning message for enabling XPROP for array corruption
AVSREQ-146007 PARSE_SV xmvlog: *F, INTERR with message vst_root () - no if_ptoroot
AVSREQ-100177 SIMVISION_DB_UTIL Various issues with simvisdbutil
AVSREQ-149177 GLS_TIMING Need to understand NTC topology reported
AVSREQ-115558 PARSE_SV xmelab: *E,TYCMPAT and *E CVMTMM
AVSREQ-151980 SV_INTERFACE xmsim crash - pwrEnableShutOff
AVSREQ-146291 UVM_ML UVM_ERROR using set_propagate_mode with UVM_ML
AVSREQ-140682 SPECMAN_TEMPORAL sn 20.09 fails to initialize integer variable to zero in compiled mode for a while loop
AVSREQ-137109 SV_GENERAL Set membership with array as range
AVSREQ-145205 MSIE_ELAB *E,OPUNSE error not showing up in user's logs
AVSREQ-103472 SV_DPI E,UNUSAG - passing unpacked struct with members that are a packed array of enums to export DPI function.
AVSREQ-138742 FUNC_SAFETY_ELAB XFS20.09/20.11 crashed with -fault_beta option
AVSREQ-153169 ELAB_PERF getting xmelab internal exception when using -newperf
AVSREQ-142846 VHDL_PARSE Error when compiling a modified VHDL STD library
AVSREQ-145300 VPI_GENERAL xcelium internal error: sv_seghandler trapno -1 addr ((nil))
AVSREQ-145099 PARSE_SV Associative array using reg: xmvlog: *E,SVEXTK
AVSREQ-141285 SIM_SV_VHDL Signal propagation difference between xcelium 20.03.002 (and earlier) and 20.09.001 (and later)
AVSREQ-99450 SIM_SV Support of exponential form in atoreal() function
AVSREQ-150043 SIM_PERFORMANCE xmelab INTERR in design that build with older version of xcelium
AVSREQ-148452 RAND_GENERAL Behavior of function in random constraint
AVSREQ-99782 VHDL_GENERAL Support for VHDL 2008 LRM feature "alias hierarchical reference"
AVSREQ-137110 SV_GENERAL E,MEM4 error information insufficient
AVSREQ-145008 ELAB_SV xmelab: *E,BNDBERR - Bit-select index is out of declared bounds
AVSREQ-143135 HAL Hal hang issue
AVSREQ-142448 LP_1801 (PICHON) Elaboration crashed with UPF
AVSREQ-118414 ASSERTION_SIM Support for string variable used in $asserton
AVSREQ-144145 SV_CODEGEN Tool throws internal error during code generation
AVSREQ-147221 SYSC_GENERAL -scautoshell does not work with -makelib
AVSREQ-98617 SV_PERFORMANCE Low Power simulation performance is slow
AVSREQ-103446 SPECMAN_COV Effect of item option "per_instance" on Gradability
AVSREQ-118332 DMS_ELAB xrun restart cannot find verilogA compilation directory
AVSREQ-146159 JUPITER_BRIDGE Xcelium multi-core crash tch_pib1_filter
AVSREQ-149168 GLS_PERFORMANCE GLS+SDF elaboration taking ~26hrs
AVSREQ-134205 ASSERTION_SVA Can -ABV_LRMCOMPLIANT_ASRTCTRL be made default?
AVSREQ-142096 ELAB_SV xmelab crash due to dpes optimization
AVSREQ-152391 DMS_ANALOG_ELAB xmsim internal exception error
AVSREQ-150897 GLS_SDF CPU performance alignment for SDF compilation
AVSREQ-150693 IP_PROTECT_GENERAL DECERR occur when using 21.05.a001
AVSREQ-144024 LP_1801 Support for Information Model propriety LIB_CELL_TYPE
AVSREQ-145029 RAND_SOLVER std:randomize() with two variables produces results which are incorrect (constraints for difference between them are ignored)
AVSREQ-129186 PARSE_SV xmvlog: *E,NULLEI error due to dos format file
AVSREQ-143250 PARSE_SV xmvlog INTERR : dtv_equivalent_type_chk () - invalid class 882
AVSREQ-87366 PROFILER_SIM_RUNTIME How to profile saved or restored simulation using the latest process based save
AVSREQ-142429 SIM_PERFORMANCE Simulator crash on simulation run phase
AVSREQ-143978 SIM_PERFORMANCE LP Simulation fails with -enable_psc_opt and -enable_deadcode_refopt
AVSREQ-73339 PARSE_SV 2094875 CCR ref event.triggered value is wrong
AVSREQ-121869 MSIE_ELAB DSSVAR error in multi-step MSIE flow
AVSREQ-139783 SIMVISION_GENERAL -replace_path in SimVision?
AVSREQ-146110 LP_1801 Elaboration crash in Low Power environment for subelem_chain_next -cannot descend to datatype
AVSREQ-147407 SV_PARAMETERS Incorrectly receiving error "xmelab: *E,NDPIFP: Defparam may not affect the range of an interface IO port."
AVSREQ-147300 XRUN_GENERAL Recompile when switch used twice
AVSREQ-100233 ASSERTION_SVA $sampled in disable iff
AVSREQ-140860 COVERAGE_CODE Expression in function not fully covered
AVSREQ-142888 SV_DATATYPES APSCNS - add support for assignment pattern in bind
AVSREQ-137077 COVERAGE_CODE xcelium treats $bits function differently in coverage mode
AVSREQ-149993 GLS_PERFORMANCE MTRANTO warning and error depending on condition.
AVSREQ-154481 ELAB_SV Xcelium is not returning correct paths to Indago, hence Indago is not able to find the source files
AVSREQ-138189 SV_GENERAL PCRFUP for associative array in ref port
AVSREQ-142413 PARSE_SV INTERR with propfile_vlog source_debug
AVSREQ-149516 DMS_LP_AMS Reduce LPX overhead on customer design
AVSREQ-138351 SV_DPI xmvlog: *E,UNUSAG Error while xcelium migration
AVSREQ-145039 SIM_PERFORMANCE Consolidated EHF e194 test fails with -enable_var_opt_core
AVSREQ-141620 DMS_WREAL Tool crashed during xmvlog_cg
AVSREQ-150800 GLS_PERFORMANCE Elaboration time improvement for in-house customer design
AVSREQ-138977 LP_1801 Supress all messages (error, warning, notes) that are not related to low power
AVSREQ-146447 DMS_LP_AMS LP MS: Bidirectional Switch with wrealavg resolution is not calculating correct voltage
AVSREQ-141242 DMS_AXUM Issue with probe to analog content with SystemVerilog bind to SPICE in Mixed Signal Simulation
AVSREQ-106973 SV_GENERAL $inferred_clock system task used
AVSREQ-144598 SIMVISION_CONSOLE SimVision console is stuck while searching with the text box
AVSREQ-145204 PARSE_SV *F,INTERR: INTERNAL EXCEPTION -if_modify_structure - New type (651) is larger than the old type (565)
AVSREQ-148737 SR_BACKDOOR Probable memory leak in solver in CX mode
AVSREQ-139758 PARSE_SV xmelab TYCMPAT error with parameterized modules and $bits usage
AVSREQ-149405 LP_1801 query_isolation support for hybrid isolation information
AVSREQ-93134 ELAB_CLONE xmelab: *E,INCUSC: Unsupported port connection type (unsupported expression on actual) identified
AVSREQ-147089 IP_PROTECT_GENERAL Encryption causes NULLEI errors
AVSREQ-144817 GLS_PERFORMANCE "-enctran" degradation since 21.01
AVSREQ-125269 LP_1801 xmelab: *E,MULSPLY: [LPS] Multiple UPF supply (testbench.rtd_vbat.VBAT42_UPF, testbench.rtd_vbat.VS
AVSREQ-139065 PARSE_SV xmvlog: *EXPRLC and EXPSMC with constructs using inside construct
AVSREQ-151057 ELAB_PERF Design elab crash
AVSREQ-100445 PARSE_SV "side" .pak creation using ncvlog and System Verilog RTL
AVSREQ-148550 LP_1801 Why the xmlib2cdb generate the "line -1" for duplicated cell case?
AVSREQ-86945 PROFILER_SIM_RUNTIME -profile doesn't work with -process_save
AVSREQ-145481 JUPITER_COMPILER support xminitialize rand and rand_2state modes in multi-core
AVSREQ-144428 SV_INTERFACE xmelab crash on function cu_vifc_check_access with 21.03.g286Debug kit
AVSREQ-152296 ELAB_SV During elaboration, xmelab INTERR (NO ERROR for error code 0)
AVSREQ-141505 XRUN_GENERAL -xmlibdirname is not expanding $ variable in below scripting form
AVSREQ-121979 XPROPAGATION_GENERAL XPROP making signal X without cause, works with access C
AVSREQ-101035 DMS_ANALOG_ELAB DVS doesn't report error even if invalid vddnet/vssnet is provided
AVSREQ-146534 PROFILER_SIM_MEMORY Allow memdetail (or similar) to be a runtime switch
AVSREQ-142516 LP_1801 Commenting out a connect_logic_net unexpectedly causes a port to go z'
AVSREQ-150740 LP_1801 set_port_attribute does not work on unconnected ports
AVSREQ-141733 LP_VHDL Enhance request for LP VHDL report
AVSREQ-135088 DMS_AXUM Undefined model found by analog solver because of sv binding definition
AVSREQ-144676 DEBUG_PROBE SST2ER: SST2 interface error: Series sort buffer maximum size reached
AVSREQ-152677 MSIE_ELAB AutoMSIE : OPPNSE error with OOPR to enum.method call
AVSREQ-148817 RAND_SOLVER Support start/end delimiters for multiline *W,*E,*F,*N messages in Randomization code
AVSREQ-148146 SIM_PERFORMANCE $deposit not triggering waveform or downstream update
AVSREQ-145701 ELAB_SV Elaboration failure due to name clash between parameter override (-gpg) and enum element
AVSREQ-123677 ELAB_SV Relaxation for NONOWD error with -xlm_bq1 -vlogrelax only for first occurrence
AVSREQ-148843 SV_PARAMETERS xmelab crashing with MESSAGE: sv_seghandler - trapno -1 addr((nil))
AVSREQ-143321 LP_1801 Enable the change of AVSREQ-138931 with a switch
AVSREQ-100902 ASSERTION_DEBUG total failed assertion count
AVSREQ-144188 SPECMAN_E Invalid pointer encountered by GC at runtime
AVSREQ-142603 LP_1801 Support for UPF_ROOT_SUPPLY
AVSREQ-144177 DMS_ANALOG_ELAB AMS analog signal becomes zero at certain hierarchy level
AVSREQ-149813 ELAB_PERF elab is 10x slower with -access r and no -access option in customer design
JIRA ID COMPONENT SUMMARY
AVSREQ-145942 SPECMAN_COV Specman does not error for non-existence of cover group kind
AVSREQ-147725 MSIE_PERFORMANCE Multi-xrun simulation perf - global module pessimism
AVSREQ-144440 DMS_ASSERTIONS FVCADCDN-4619 : Xcelium_Option:- Testcase getting crash with xcelium option -show_rnm_cover at elaboration phase.
AVSREQ-134354 LP_CPF [PA RTL] Use of -lps_reg_mfile causes elaboration to quit skipping the final snapshot creation, causing simulation failure
AVSREQ-147065 DMS_ELAB xmelab INTERR: sv_seghandler - SIGSEGV while handling SIGSEGV
AVSREQ-148266 GLS_GENERAL different simulation behavior when VCD format waves dump
AVSREQ-101389 ESW_SYMBOLICDEBUG Display of union type with bit field is incorrect in Indago ESWD
AVSREQ-148174 ASSERTION_DEBUG asrctl message in one line
AVSREQ-142291 DEBUG_DESIGN_DATABASE Wrong signal name representation in waveform window on packed struct member select
AVSREQ-142534 LP_1801 LP-NORTELE error occurrence at Xmelab
AVSREQ-148086 ASSERTION_PERFORMANCE Migration: Assertion performance enhancement is needed to improve CPS gap
AVSREQ-148036 CORE_SV_IN default perf switch da_two_stated_mem_opt causing test fail
AVSREQ-140004 JUPITER_COMPILER South crash due to a circle created by power gaters optimizations
AVSREQ-145868 SV_GENERAL Migration: bit repetition fails in ternary expression with streaming concatenation
AVSREQ-147664 LP_1801 Log file enhancement for sim2clp with -lps_net_split
AVSREQ-99433 SIMVISION_DB_UTIL Simvision abort when trying to export - full fix
AVSREQ-139389 FUNC_SAFETY_ELAB Internal exception error during elaboration with "-fault_beta" option
AVSREQ-138896 DMS_AXUM bind on spice automatically impossible with vcfg_no_default_bind
AVSREQ-88717 ELAB_SV Add option to allow initializations as one of two drivers (for FPGA synthesis).
AVSREQ-138780 SV_PERFORMANCE improve performance for big testbench bottleneck
AVSREQ-145971 LP_CPF Iso control condition maintained while condition is inactive
AVSREQ-142614 XPROPAGATION_GENERAL xprop report with systemC TB generates a wrong report
AVSREQ-119259 DMS_LP_AMS Two supply nets in UPF scope are connecting to the same HDL(wreal) signal results in xmelab: *E,CSNMCN
AVSREQ-152257 SV_GENERAL wrong sign expansion and operation
AVSREQ-130278 PROFILER_XPROF Iprof should plot run time and memory vs wall clock time
AVSREQ-152088 DEBUG_DESIGN_DATABASE Indago source browser showing values in one instance only (other instances missing)
AVSREQ-153320 SV_PERFORMANCE *F, INTERR, sv_seghandler with -enable_cb_ddce
AVSREQ-147195 LP_1801 xrio should be updated with additional switches for interface support
AVSREQ-93324 SIM_SV SVTPOU error when using mailbox in uvm_config_db
AVSREQ-152156 PROFILER_SIM_RUNTIME Enhance the reporting of memdetail for MEM_DETAIL_REPORT_LIMIT
AVSREQ-151375 GLS_SDF sdf_ignore_simvhdl does not fix SDFSVIT
AVSREQ-140968 SIM_FORCE_RELEASE "force" assignments do not happen in the generate "for" loop with xrun
AVSREQ-151686 SIM_PERFORMANCE *F, INTERR, sv_seghandler
AVSREQ-152171 MSIE_ELAB add support of OOPR for mixed-language design
AVSREQ-151116 DMS_BIND Request to downgrade EXANCU error to a warning if -dms_fast_debug option is enabled
AVSREQ-143120 SV_PERFORMANCE Xcelium skips task line unless nearby $display or -linedebug
AVSREQ-143348 DMS_ANALOG_ELAB Unexpected OBANOVL 'object does not exist' error for nets
AVSREQ-141348 SV_ALL atoreal removing - sign when ^M is at the end of the number
AVSREQ-144661 PROFILER_SIM_RUNTIME xmprofmerge profile data doesn't match the actual profile data
AVSREQ-147630 IP_PROTECT_GENERAL xmprotect results in encryption that you cannot browse waveforms even with -simulation debugall with certain compiler directive/macros defined.
AVSREQ-136402 MSIE_ELAB MESSAGE: sv_seghandler - trapno -1 addr((nil))
AVSREQ-148054 COVERAGE_PERFORMANCE xmelab taking ~5 hours on ixcom generated model
AVSREQ-145001 FUNC_SAFETY_CONCURRENT Support always @(*) having more than one unpacked memory in reference
AVSREQ-151084 DMS_AXUM *E,AMSMDA error for multi dimensional array to spice connection
AVSREQ-144391 FUNC_SAFETY_CONCURRENT fault is DU in serial and UU in concurrent
AVSREQ-130551 ELAB_BIND Limit the scope of warnings
AVSREQ-150095 ASSERTION_PERFORMANCE always_comb gives wrong results when using structs
AVSREQ-132671 ELAB_SV BNDWRN - Message enhancement to show instance hierarchical path, array size and bit select range
AVSREQ-139932 SV_GENERAL CUVNPM error when $bits() is used with hier path in a SV bind context
AVSREQ-119751 SYSC_GENERAL scautoshell does not support modules not compiled into the worklib
AVSREQ-147885 PARSE_SV incorrect invalid type error
AVSREQ-121385 SIM_CAPTURE_REPLAY Insert fixed delay on specified signals during replay
AVSREQ-146096 LP_1801 Support for upf_generic_pre_iso
AVSREQ-131604 LP_1801 support all assertion control in liberty model through create_assertion_control -lib_model {*}
AVSREQ-76588 SIM_SV mailbox as class type param
AVSREQ-143086 SV_GENERAL BSCXSZ Error
AVSREQ-146772 SIMVISION_MS Need equivalent TCL command for Browse Currents
AVSREQ-112202 PARSE_SV Please support `wrealXState and `wrealZState as legal values for System Verilog Struct - real member initializer
AVSREQ-150359 DMS_LP_AMS WUDNPFS for set_port_attribute reference on an intermediary port
AVSREQ-133383 SV_GENERAL E,ILLPRI Error at customer end
AVSREQ-149756 ELAB_SV Tool crash with message vst_immediate_scope() - bad class
AVSREQ-152106 DMS_BIND INTERR in check_is_svvhdl_mixoomr_and_resolve
AVSREQ-150865 DEBUG_DESIGN_DATABASE Indago does not load and hangs on the Cadence logo on some farm machines
AVSREQ-147318 PARSE_SV Improve xmvlog MACRDF warning message to include prior define location
AVSREQ-143977 SIM_USABILITY Xmsim : Message: sv_seghandler: dynamic out-of-bounds wait on an expanded wire
AVSREQ-148935 SV_CODEGEN Large enum.next() handling is too slow
AVSREQ-125551 DMS_WREAL *F, INTERR with message "gq_vload_defval - not a vector"
AVSREQ-139515 SIM_PERFORMANCE xmelab INTERR: Always pruned, but register did not qualify
AVSREQ-105580 SV_GENERAL Support for 'with' expression in streaming concatenation, xmvlog: *E,SOWUNS
AVSREQ-148353 COVERAGE_SIMULATION Different simulations results with coverage.
AVSREQ-108688 XPROPAGATION_GENERAL remove XPWDIS message in xp_elab where -xverbose exists
AVSREQ-146516 GLS_GENERAL IOPATH timing altering with and without VCD dumping
AVSREQ-138429 SV_DPI UNSUAF error with DPI-C error and shortreal
AVSREQ-133926 ASSERTION_SVA xmvlog: *E,SFLNOS (SFLNOS.sv,12|53): SystemVerilog streaming concatenation operator in this context is not supported.
AVSREQ-152685 ELAB_SV xmelab INTERR: NO ERROR for error code 0
AVSREQ-145471 LP_1801 bind_checker.sv is not created if added -lps_cov.
AVSREQ-141240 LP_1801 balloon style register is not corrupt when retention supply becomes corrupt + Retention enable signal is not being corrupted when toggling during CORRUPT_ON_ACTIVITY
AVSREQ-141160 SIM_CAPTURE_REPLAY Enhance XMREPLAY_SIGNAL_REPLAY_FILE to support inversed value replay
AVSREQ-152376 GLS_PERFORMANCE "-suptran" option requires "-access +w" to be applied.
AVSREQ-147816 SV_INTERFACE CUIMBC ELAB ERROR related to 3rd party VIP
AVSREQ-147688 RAND_GENERAL No VALFIT warning for nested class constraints
AVSREQ-120369 SV_PORTS Support event argument to a module
AVSREQ-138708 PARSE_SV xmvlog should be able to handle dos characters in source files
AVSREQ-100135 SV_GENERAL default port value support
AVSREQ-148040 GLS_GENERAL xmsim crashes with the message SSS_MT_FRZ_BYTE
AVSREQ-145055 SV_GENERAL lwdgen causes elab to hang
AVSREQ-148365 JUPITER_BRIDGE JUP_pATPG_DSS : 35x degradation in incremental elaboration, nacc_analysis stage exploding and taking 23hrs
AVSREQ-144401 SIM_PERFORMANCE Optimizing latch where registers with different bits are shared in different latches
AVSREQ-132293 SIM_PERFORMANCE Always latch not being pruned
AVSREQ-145395 SPECTRE_AMSD Two xcelium.d directories get created when -xmlibdirname argument is used with FLEX
AVSREQ-145989 GLS_GENERAL Build crash with 21.03-a001 debug kit
AVSREQ-145487 MSIE_ELAB Another -nolog issue with MSIE
AVSREQ-111251 ELAB_SV xmelab *E,QDANBA error.
AVSREQ-147384 PARSE_PERF Performance degradation with -librescan option
AVSREQ-149078 SPECMAN_E Bad enum value for 'numeric_format_kind' when printing numeric type with radix setting
AVSREQ-149000 COVERAGE_CODE simulator hangs with coverage enabled
AVSREQ-148734 SPECTRE_AMSD Name a digital event by the event index: digital changes for CCR2488607
AVSREQ-145936 GLS_GENERAL simulator different behavior 20.09.007 -> 20.09.010
AVSREQ-152694 XPROPAGATION_GENERAL *F,INTERR: INTERNAL EXCEPTION is coming out with using the xprop -c
AVSREQ-138451 SV_BUILD_PERF elab consistently slows down, memprof attached
AVSREQ-147295 PARSE_SV Positional parameters handled incorrectly for local type param
AVSREQ-143690 SV_DPI DPI issue while using SvBitVecValue in C functions
AVSREQ-148293 IP_PROTECT_GENERAL Xcelium report error when perform "memory -load" with a memory in protected IP
AVSREQ-147293 SV_GENERAL FJNRFA not reported on function resolved through type param
AVSREQ-147926 LP_1801 Crash due upf_get_value_str call for a LIB_CELL_TYPE handle
AVSREQ-137306 XRUN_GENERAL xrun -timescale -compile should flag a warning
AVSREQ-144390 LP_1801 [PUNIT] LPS - streaming concat breaking functionality
AVSREQ-151755 ELAB_SV During elaboration, xmelab INTERR (ivia_pair_sanity_check - vst and ot mismatch for vst class)
AVSREQ-145235 SPECMAN_UVM_E uvm e vr_ad : update( ) call from write_reg_raw() changes the direction to be WRITE inappropriately
AVSREQ-143461 LP_1801 Support for the key: location in query_isolation
AVSREQ-102428 DMS_ELAB EEnet package should take of EEnet nettype as logic and wrealsum (custom)
AVSREQ-145660 VPI_PLI AMS co-simulation crash with fatal error SIGUSR Unix Signal SIGSEGV with specman interface
AVSREQ-143237 SV_PORTS Elab enable read access of ref port variables in $writememb/$writememh
AVSREQ-136946 SPECTRE_AMSD Simulation failure due to VHDL Alias usage in MS context
AVSREQ-146685 RAND_DEBUG Constraint debugger does not take to the correct TLP bucket where the variable is solved
AVSREQ-150443 SPECMAN_E C FLI mapping of uint(bits:33-64) into C uint64_t
AVSREQ-148102 SIM_SV_VHDL wrong OOMR assign value to record when field initiated with function
AVSREQ-144673 LP_1801 To track CCMPR02459003 (another issue found in UPF-linter in case apply_power_model inside power model)
AVSREQ-105449 SV_GENERAL Support for bitstream operator in assignment to dynamic array
AVSREQ-151331 LP_VPI LWD failure on customer LP design
AVSREQ-92651 SIM_SV ncvlog: *E,SVTPCO (): Currently type parameter override is not supported for this datatype.
AVSREQ-105058 SV_GENERAL Xcelium stream operation does not support "with"
AVSREQ-149433 LP_1801 Power model with supply state and logic expression in add_power_state corrupts VSSE pin
AVSREQ-144285 LP_1801 Query should return primary_power_net key based on isolation location.
AVSREQ-157734 ELAB_BIND Xcelium elaboration fails with xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-128927 PARSE_SV support for module name exceeding 1023 characters
AVSREQ-136024 PARSE_SV Option to downgrade PMBNOB error to a warning
AVSREQ-144778 SIM_SV xmsim INTERR: svvi_get_stream - stream not found
AVSREQ-138352 DMS_ELAB add more support to dms_report option
AVSREQ-73650 SV_PORTS Fatal Error when using -primtop
AVSREQ-105392 SV_GENERAL Xcelium stream operation does not support "with"
AVSREQ-152079 ELAB_CLONE xmclone: *E,INCUSC for {OOMR, enum-literal} in port expression
AVSREQ-144997 XRUN_MSIE elaboration crash with autoreplicated_top
AVSREQ-132598 COVERAGE_CODE Enhancement request to support code coverage on expressions involving "inside" construct
AVSREQ-101568 SV_GENERAL Module port default values not working
AVSREQ-152904 FUNC_SAFETY_ELAB XFS is crashing at elab time with -fault_rtl switch
AVSREQ-133691 JUPITER_HVIEW MC_EVAL_BUILD_PERF: 1.4X elaboration memory overhead with mce_hview
AVSREQ-147494 PROFILER_SIM_MEMORY memory profiler doesnt show memory allocated at c using chandle
AVSREQ-137764 SIMVISION_WAVEFORMS loading to simvision svwf with changes breaks
AVSREQ-140105 SV_INTERFACE abnormal shm signal value dump in Dynamic Test + LP sim
AVSREQ-144855 MSIE_ELAB [MSIE] xmelab: *E,IEPKGF: Package not shared between partitions. [solved]
AVSREQ-136045 VHDL_PARSE SIGPUP (Signal expressions on unconstrained port) error
AVSREQ-143549 CORE_RAND Solver crashes with the new Xcelium solver, Solves successfully in legacy solver
AVSREQ-139633 PARSE_SV ILLGVR, This genvar cannot be used in this context
AVSREQ-153271 SIM_USABILITY No EndError EndWarning reported with option -enable_msg_marker with xmvlog
AVSREQ-135874 LP_1801 support of apply_power_model inside a power model is missing
AVSREQ-151738 DEBUG_DESIGN_DATABASE Indago exits unexpectedly with a memory error during interactive debugging
AVSREQ-155345 SIM_PERFORMANCE Internal exception during elaboration with 21.03.v005
AVSREQ-153292 SIM_CAPTURE_REPLAY 'XMReplay' spell wall warning : agile/xcelium
AVSREQ-145685 SIM_PERFORMANCE Xcelium RTL compile – stack trace while using 21.02-a001
AVSREQ-137643 SIM_TCL Enabling thread support in TCL + bundle TCL Thread Extension package in our installation
AVSREQ-138565 DMS_ELAB dms_report file is not getting generated withtout rnm_coerce and disres switch
AVSREQ-151225 SIM_PERFORMANCE Simulation hang at time zero with newperf switch enable_alcomb_ext_opt
AVSREQ-126254 XPROPAGATION_GENERAL X-Propagation Disabled for Call to procedure in VHDL
AVSREQ-140203 JUPITER_RTL_SC MC build crash while MC split
AVSREQ-146875 CORE_RAND Randomization engine producing incorrect values due to issues with function calls
AVSREQ-119262 LP_1801 p/nwells connected to supply nets/ports vdd_24v/gnd_24v not getting the voltage
AVSREQ-153068 SPECMAN_E Internal Assertion triggered when using TLM ports with templates of value parameters and hex radix
AVSREQ-141106 COVERAGE_SIMULATION Throw an error for using optimize_dump in ccf
AVSREQ-152329 SIM_SV Wrong behavior of sting concatenation operator
AVSREQ-147218 SV_GENERAL CLSSVN when using non blocking event triger
AVSREQ-111637 SIM_PERFORMANCE VTW not converting intf signals, cont assignments appearing in xmprof
AVSREQ-141094 SPECMAN_METHODOLOGY vr_ad_mem alloc - assumes size is int
AVSREQ-142590 LP_1801 Support for upf_query_pg_info(hdl_path, "", UPF_PRIMARY_POWER_PGTYPE)
AVSREQ-121380 SIM_CAPTURE_REPLAY Replay specified signals after inverting them
AVSREQ-149866 SPECMAN_COMPILE Internal Error when creating elib with sn_compile.sh
AVSREQ-146112 PARSE_SV Enhancement req. about stream op. with ternary op.
AVSREQ-145973 PROFILER_XPROF ".xmprof_summary.out" mismatches the gui result of xprof.
AVSREQ-138526 LP_SV Low power probing incorrectly creates probes inside of protected region
AVSREQ-151272 RAND_DEBUG Can't see array values when using an index
AVSREQ-126152 FUNC_SAFETY_CONCURRENT performance issue with concurrent engine on a given campaign
AVSREQ-134375 LP_1801 Support for set_port_attribute reference to create_logic_port signal
AVSREQ-136977 HAL not queuing the license properly
AVSREQ-135996 SV_DYNAMIC_DATATYPES [XLM] difference behavior between alloate dynamic array in or out function
AVSREQ-149203 SPECTRE_AMSD Blackbox with dspf does not work in AMS
AVSREQ-148390 SIM_SV After reset command the always block not executing
AVSREQ-144466 DEBUG_PROBE Using ida_probe -start_time=<current time> returns an error
AVSREQ-145071 ELAB_CLONE xmclone crash with 20.03 due to $deposit in replicated hierarchy
AVSREQ-144942 SV_BUILD_PERF xmelab slowdown issue
AVSREQ-131200 LP_1801 Question about SNDRMU warning and elaboration perf issue
AVSREQ-152464 SPECMAN_SAVE_RESTORE Indago launch crash (OS signal 11) at Specman 'DA restore'
AVSREQ-153398 SV_PERF The simulation behavior is different between w/wo -newperf
AVSREQ-147783 LP_1801 associate_supply_set FSpec and implementation
AVSREQ-139422 GLS_GENERAL Support for deposit -sense_input option in $xm_deposit
AVSREQ-138688 LP_1801 1821128: xmlib2cdb creates error when interface_timing used with function
AVSREQ-156909 GLS_SDF xmsim INTERNAL EXCEPTION MESSAGE: rts_net_fse - bad stopreason (0)
AVSREQ-91358 SV_DATATYPES APSCNS - add support for assignment pattern in bind
AVSREQ-151196 ASSERTION_SVA W,ACTBDN warning changed to *E, SCPAUR when add -enable_abv_asrtctrl_enh
AVSREQ-144319 ELAB_VHDL Support generic override, -gpg, for vhdl type unsigned
AVSREQ-147505 ELAB_SV Getting DLNORD error on second run of single-step MSIE elaboration
AVSREQ-134488 LP_1801 UPFERRM is triggered when argument of -type use curly braces
AVSREQ-140122 RAND_SOLVER rts_abrthandler - SIGABRT unexpected violation pc=0x2b671bbda4f5 addr=0x7340aef900017a7a
AVSREQ-150132 SV_PARAMETERS xmelab: *F,INTERR dto_range_width - no width
AVSREQ-149351 SV_PERFORMANCE Xcelium performance is slower than competitor
AVSREQ-147736 GLS_PERFORMANCE Huge Simulation time in GLS.
AVSREQ-142469 LP_1801 *F,INTERR: INTERNAL EXCEPTION when elaboration with UPF
AVSREQ-149518 DMS_LP_AMS Reduce LPX overhead on customer design with DMS
AVSREQ-140669 SIM_USABILITY Issue with $deposit command
AVSREQ-125273 ASSERTION_SVF xmvlog: *E,SELPRV : Use of variable or variable-index in the select expression inside the sampled value function $changed is not supported.
AVSREQ-143466 LP_1801 Support for query_cell_mapped
AVSREQ-141215 PARSE_SV Erroneous xmvlog: *E,ILLHIN (final.sv,34|153): illegal location for a hierarchical name (in a package) only when using parameterized type
AVSREQ-150839 PARSE_SV xmvlog INTERR:: get_randomize_class_prefix_decl() - Unexpected prefix used with class randomize
AVSREQ-147382 IXCOM How to use VDMs for the latest VIPCAT
AVSREQ-145188 XRUN_MULTI_CORE Add xmhelp xrun entry for MCE2CON
AVSREQ-143579 CORE_RAND RNDREFA - unsupported scope randomization of ref arg
AVSREQ-145854 DMS_LP_AMS LP MS: incorrect VOLTAGE values for bidirectional switch model with wrealavg
AVSREQ-150939 GLS_GENERAL functional difference if the UDP output is probed or not
AVSREQ-149823 PARSE_SV Please improve PANOTL error
AVSREQ-146496 XPROPAGATION_GENERAL Provide XPROP support with case expression width > 64 bits
AVSREQ-147495 SIM_SV Simulation is stuck at sort() SV function
AVSREQ-144246 SIM_PERFORMANCE *E,BDOPT on newperf opt switch -enable_varca_stream_opt
AVSREQ-150042 DMS_ELAB Elaboration crash with SystemVerilog assertion pointing to vst_expr and cag_get_driving_expr (when using inherited connections mixed signal algorithm)
AVSREQ-149705 SIM_VHPI need support for VHPI to work in uVisa mode with OTs
AVSREQ-143469 LP_1801 lps_time0_isox glitch
AVSREQ-140148 ASSERTION_SVA Unexpected ASRTST message
AVSREQ-152851 DMS_LP_AMS internal exception when UPF function find_objects is applied on SV-RNM User Defined Nettype
AVSREQ-145761 DMS_LP_AMS CPF shutoff condition with electrical expression shows *E,WCNDINO
AVSREQ-102479 SIM_SV_VHDL Request OOMR write support for VHDL record and record elements
AVSREQ-138966 SIM_SV Demote $error - *E, ERRSEV to have an exit status '0'
AVSREQ-99128 LP_1801 extend lps_cov to cover also add_power_state
AVSREQ-148399 SPECMAN_COV Cadence/XCELIUM/21.02.001- Running Specman testbench faulier
AVSREQ-119882 PARSE_SV unused library in cds.lib gets unnecessary pak file created
AVSREQ-139447 SIM_VHDL failing to describe memory
AVSREQ-149619 VPI_PLI VPI Internal error on uvm_hdl_force
AVSREQ-142762 UVM_ML_OA_INSTALL SPECMAN_DLIB should no longer be dumped into setup.* when building UVM-ML-OA
AVSREQ-145030 PARSE_PERF sv bind consumes memory 10 times.
AVSREQ-150001 LP_1801 set_design_attributes -elements <element_list> UPF_dont_touch not honored
AVSREQ-142970 JUPITER_COMPILER *F,MCEASRT: Multi-core elaboration assertion 'An expanded template signal 'N' of width '5' has wrong number of template vars
AVSREQ-144445 XRUN_GENERAL fast_recompilation prevents elaboration from re-elaborating
AVSREQ-152326 JUPITER_ENGINE wave dump optimisation for optimized out egress
AVSREQ-145852 PARSE_SV INTERR dt_is_array hit unknown datatype (VST_T_TYPE_PARAMETER)
AVSREQ-129214 ASSERTION_SIM Several false failures of an assertion during simulation
AVSREQ-134608 XRUN_GENERAL single quotes added to SPECMAN_PATH prevents Specman restore
AVSREQ-132953 GLS_GENERAL unexpected behavior of verilog primitive
AVSREQ-151634 SV_GENERAL GLS simulation crash when running with -ENTCHGROUP
AVSREQ-143502 LP_1801 Automatic lib2cdb conversion tries to write to read-only directory
AVSREQ-151711 XPROPAGATION_GENERAL Provide debug information with side-effect methods
AVSREQ-147605 SV_CODEGEN Simulation differences in +access+rw vs afile runs. -disableopt leads to code generation crash
AVSREQ-140804 SAVE_RESTART_DMTCP Segmentation fault on user code when restoring on a machine with different arch
AVSREQ-143119 SV_PERFORMANCE Xcelium Optimization Bug - line of task ignored without a $display() or -linedebug
AVSREQ-145622 JUPITER_BRIDGE CAG is causing more HardEgress when run with "-access +r"
AVSREQ-146177 DMS_AMSD *E, AFHDWT (…) Elaboration error with analog_node_alias()
AVSREQ-147387 FUNC_SAFETY fs_strobe parsing issue: signal defined as a checker strobe is listed as a functional strobe in FLDT detection message
AVSREQ-146081 DEBUG_DESIGN_DATABASE Indago becomes unresponsive
AVSREQ-146489 SIM_TCL 'deposit -scope' command fails when called from a sourced TCL script
AVSREQ-150404 GLS_TIMING sv_seghandler - trapno -1 addr(0x1fc)
AVSREQ-149815 SIM_USABILITY xmsim: *E,OBJACC: Object must have read access: <…signal name…>
AVSREQ-119397 ELAB_SV xmelab: *W,CUVIHR :: when reference is made to generate item present inside interface
AVSREQ-148387 RAND_SOLVER Unexpected randomization result
AVSREQ-151308 SPECMAN_DEBUG OS signal 11 using Specman debugger
AVSREQ-148187 VWDB to support auto-update
AVSREQ-138989 DMS_WREAL xmelab internal error when coverage enabled: rts_abrthandler - SIGABRT unexpected violation
AVSREQ-140729 DMS_LP_AMS support vct mapping for wrealZState to UPF net
AVSREQ-146529 SIM_USABILITY Create an identifying tag to indicate if warning and error messages span multiple lines
AVSREQ-142616 PARSE_SV import DPI inside of a generated if statement causes compile error
AVSREQ-115112 PARSE_SV xmelab: *E,CUVUNF (adapter.sv,554|20): Hierarchical name component lookup failed for 'resp' at 'nitro_axi_pkg'
AVSREQ-141204 ASSERTION_DEBUG internal error while changing assertion via assertion tcl cmd
AVSREQ-155368 SIM_PERFORMANCE INTERNAL EXCEPTION during elaboration
AVSREQ-147228 SV_PORTS xmelab: *E, PCIONC - Expression connected to an 'inout' port must be collapsible.
AVSREQ-147888 PARSE_SV Reported line numbers mismatch for CUVUNF
AVSREQ-151579 JUPITER_COMPILER Override delay mode for specific path in MC
AVSREQ-144607 SV_GENERAL customer migration: macro code for ternary expression , wrong functionality
AVSREQ-136161 XPROPAGATION_GENERAL REGSOV elab error when applying Xfile
AVSREQ-150106 LP_SV xmelab: *E,STRMOP: [LPS] Stream concat operator failure: offset/size incorrect
AVSREQ-143703 LP_1801 Support for the key primary_power_net in query_retention
AVSREQ-141216 VPI_LWD indago takes 4 minutes to open UVM hierarchy
AVSREQ-152643 SPECTRE_AMSD Flex 2.0: block any analog tcl command once users shut down Spectre process via 'exit -analogsolver'
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AVSREQ-144825 UVM_SV uvm command line processor is unable to read command line arguments when XMSIMOPTS environment variable is set
AVSREQ-141776 PARSE_SV Non-printable characters instead of filename in error message
AVSREQ-144342 ELAB_SV xmvlog: *E,NONOWD, Illegal use of a constant without an explicit width specification
AVSREQ-149645 SIMVISION_GENERAL Crash issue in Cross probing between VSE and SimVision
AVSREQ-149808 PARSE_SV generate error message instead of a crash
AVSREQ-141229 PARSE_SV xmvlog INTERR Unexpected Signal #11
AVSREQ-152207 LP_1801 bind_checker doesn't support multiple indexes
AVSREQ-143715 XM_UTILS_GENERAL xmgentb -selfchk does not generate a correct self-checking testbench
AVSREQ-143678 GLS_SDF internal error when using sdf_simtime to annotate sdf in sim time
AVSREQ-143344 SV_GENERAL disable iff assertion fail while it should not
AVSREQ-141655 LP_1801 Isolation cell is not inserted with -lps_net_split
AVSREQ-152414 LP_SV interface inout ports values not updated in UPF simulation
AVSREQ-145501 COVERAGE_FUNCTIONAL Enhance COVLNB warning to include cross/coverpoint count
AVSREQ-116654 SV_GENERAL -vlogcontrolrelax NOTPAR doesn't work
AVSREQ-122334 ELAB_SV xmelab: *E,MULAXX Multiple drivers to always_ff output - with variable declaration initializers
AVSREQ-148162 SIM_PERFORMANCE Elaboration crash in Modem environment for ivia_rpackage_dereference-NULL instance
AVSREQ-119972 SIM_SV inverter output stuck 0 for some time peoriod.
AVSREQ-136379 SIM_USABILITY CUNOBJ information insufficient
AVSREQ-149970 MSIE_SIMULATION Randomisation + MSIE bbox flow - error during simulation
AVSREQ-132889 COVERAGE_TOGGLE packed struct is not showing as completely covered
AVSREQ-151281 ELAB_SV xmelab crash related to vst_immediate_scope() - bad class, class 623
AVSREQ-153278 DMS_ANALOG_ELAB xmsim: *E,SYERROR occurs only when analog object(Verilog-AMS instance) in SV module(with local param)
AVSREQ-134803 SV_GENERAL Initialization of dynamic array not applied on new declaration
AVSREQ-133372 SV_PERFORMANCE xmsim size keeps growing
AVSREQ-149817 ELAB_PERF simulation difference with -gpg_sim when overriding value at simulation
AVSREQ-118629 LP_1801 Same supply net connection in UPF and RTL
AVSREQ-123954 ELAB_SV *W,BNDWRN: Support wire type - bit select out of boundary
AVSREQ-150946 SIM_PERFORMANCE Please print -disableopt individual flags in log and -stdout_option output
AVSREQ-144657 LP_1801 Enhancement on LIBINLIB to automatically connect inside liberty as always_on.
AVSREQ-141442 SIMVISION_MS SimVision: Connect modules are missing in Schematic Tracer
AVSREQ-148690 LP_1801 files generated with "-lps_cov" have compile issues…
AVSREQ-100802 LP_1801 supply net connected to inout in module
AVSREQ-137112 SIM_SV heap report tcl command does not report reference in class tasks
AVSREQ-147240 LP_1801 Supply net GND is not connected to upper level DVSS
AVSREQ-146341 JUPITER_BRIDGE Requesting $countdrivers and $showvars support
AVSREQ-134833 LP_1801 Isolation cell for split net insertion is not expected
AVSREQ-144353 DEBUG_PROBE Using ida_probe -start_time=<current time> returns an error
AVSREQ-150403 ELAB_DOC Question about the description of -caint
AVSREQ-146942 VPI_GENERAL vpiTimePrecision wrong computation
AVSREQ-145326 SPECTRE_AMSD IP Export Reuse flow with xmlibdirpath give ERROR (SFE-868) "nosuchfile.sp"
AVSREQ-153044 ELAB_VHDL xmvhdl_cg internal exception gq_psunlink - missing succ when migrating IXCOM flow to Xcelium 20.09-s013
AVSREQ-151011 SAVE_RESTART_DMTCP Xcelium is crashing on specific CPU platform
AVSREQ-152317 SIM_PERFORMANCE ELAB CPU degradation with super_prune optimization
AVSREQ-154393 ELAB_PERF Xcelium build takes 108GB without -ENABLE_PSC_OPT
AVSREQ-149278 SIM_PERFORMANCE Internal Error (gq_ttold - switch followed by CUVCGF) during xmvlog_cg
AVSREQ-116742 SIM_USABILITY Support -nowarn LDVAL
AVSREQ-148728 SIMVISION_GENERAL E,UNKOPT: unrecognized option for the simvision command (-title)
AVSREQ-145221 SIMVISION_MS Current Browser: Create Probe from Browse Currents fails
AVSREQ-142382 LP_SIM_PERF Xmsim crash at SimTime 0 with ENABLE_PSC_OPT
AVSREQ-96162 DMS_AXUM AXUM: Enable connection of multi-dimensional array or vector to electrical port
AVSREQ-106626 MSIE_ELAB Need of "-congruency" switch in MSIE flow
AVSREQ-139400 SPECMAN_TEMPORAL Wrong behaviour of nested 'all off' and 'all of for' in a TCM
AVSREQ-102437 DMS_ELAB Elaboration error *E,CICAPC
AVSREQ-144889 SV_CODEGEN Intel SoC: tool Fatal on elab
AVSREQ-135432 DMS_ANALOG_ELAB lost analog bus OOMR connection using SV file without port
AVSREQ-153921 DEBUG_DESIGN_DATABASE LWD database enhancements cause regression builds to hang at customer
AVSREQ-151889 LP_1801 The find_objects command returns no objects *N, FOOESR
AVSREQ-141857 DMS_LP_AMS Plans for enhancing interface support for CPF
AVSREQ-146592 ELAB_BIND CUIMBC when trying to implicitly connect interface port to another bound unit
AVSREQ-145126 CORE_RAND Possible bug in multi-pass causing constraint contradiction
AVSREQ-142343 SIM_VHDL Simulation Crash using vhdl_seq_nba but no crash with vhdlsync
AVSREQ-154299 DMS_LP_AMS Elaboration tool crash Design contains WREAL models + CPF.
AVSREQ-148031 COVERAGE_FUNCTIONAL Disabling Functional coverage during compile time
AVSREQ-151870 SIM_PERFORMANCE xmelab *F,INTERR: INTERNAL EXCEPTION tl_elwait_count_expr - bad expr 850 VXT_E_UNKNOWN
AVSREQ-151931 RAND_SOLVER Unexpected randomization results with new tool version.
AVSREQ-151647 DMS_LP_AMS ILOBJUE message created for a signal that exists
AVSREQ-144411 SIM_PERFORMANCE xmelab: *F,INTERR: tl_analyze_pib_usefulness - live pot dftSmsPipeline1_adl maps to dead pib OT with -redinline
AVSREQ-146900 SPECMAN_ERRORS Recursion during signal handling
AVSREQ-144672 ELAB_BIND MSIE with VHDL configs does not work
AVSREQ-153696 DMS_ELAB SIEDTM error using scalar connections(x) to SIE Input port specified as wire [0:0] x
AVSREQ-150367 LP_1801 Elaboration crash for Modem MSS Low Power environment, nettmp_kind -null nettmp
AVSREQ-128086 UVM_ML_SYSC bug in uvm_sc adapter
AVSREQ-81574 COVERAGE_CODE exclude coverage of methods called from pragma coverage off regions
AVSREQ-148416 DMS_LP_AMS WUDNPFS error for no_isolation specification for a coerced net
AVSREQ-137961 SIM_SV probe -screen displays incorrect value for signal which should be XXX under shut off condition
AVSREQ-144143 LP_SV comb. always block is replayed at power-up while it should not
AVSREQ-147338 RAND_GENERAL Randomization crash in MSIE flow
AVSREQ-93548 SIM_SV *E, SVTPOU: Currently type parameter override is not supported for this datatype (mailbox)
AVSREQ-138003 ASSERTION_SIM -enable_var_opt_core causing simulation Error on final immediate assertion
AVSREQ-106456 SV_PERF $sdi_set_attribute_by_name consuming CPU cycles
AVSREQ-146130 SV_PERFORMANCE Clocking Blocks on runtime performance
AVSREQ-144658 LP_1801 Support on VCT table for PARTIAL_ON translation to '1'.
AVSREQ-148480 ASSERTION_SIM assertion takes a lot of memory on sv heap, doesn't seem to clear
AVSREQ-147048 LP_1801 xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-141583 LP_1801 Make option -lps_vhdl_reg_opt default
AVSREQ-93232 ASSERTION_SVA Assertion failures when the disable iff is active at the prepond region
AVSREQ-145380 SIM_USABILITY Elaboration performance degraded with a newer version of agile, 21.02-a(2x)
AVSREQ-148841 JUPITER_BRIDGE JUP_pATPG_DSS: Elaboration crash in incremental. Degradation w/ 21.04-a001.
AVSREQ-118534 SPECTRE_AMSD VoltusFi+AMSD+Xcelium Flow: Support blackbox module in dspf_include - when it is configured to Verilog/HDL
AVSREQ-152444 LP_1801 Retention is not obeying set signal
AVSREQ-143451 VPI_GENERAL ERROR: VPI NOPTVAL vpi_put_value() cannot place a value into the object of type vpiPartSelect.
AVSREQ-134320 ELAB_SV Enhancement to support custom format for elaboration $info messages
AVSREQ-146241 LP_BUILD_PERF XMELAB: LSNDHDL-LPS warning occurrence
AVSREQ-113321 LP_1801 Implementation - UPF supply net & port re-architecture
AVSREQ-142484 GLS_SDF The RETAIN timing arcs are ignored when the SDF annotation is performed dynamically.
AVSREQ-152894 SIM_PERFORMANCE change MEMIND to MEMPC when memopt and IDA/probe is used
AVSREQ-144763 SIM_PERFORMANCE removing -enable_dotstar_var_tlg_assoc from newperf - 21.03.v001
AVSREQ-142277 SIM_SV Xcelium crashes when doing reset from Indago gui
AVSREQ-140031 CORE_SV_IN Systemverilog fork-join statement activation issue (new error scenario)
AVSREQ-130205 FUNC_SAFETY_CONCURRENT 8x+ overhead when using the BADEL optimization
AVSREQ-147395 PARSE_SV fatal error on compilation when using -enable_strict_macroref
AVSREQ-152192 SIM_PERFORMANCE newperf with -disable_alcomb_ext_opt not working effectively
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AVSREQ-88954 SV_GENERAL xmvlog: *E,SOWUNS (testit.sv,18|22): with expression in streaming concatenation is not supported
AVSREQ-139054 ELAB_BIND xmelab: *E,CUVUNF - bind to module.instance.hierarchy not allowed
AVSREQ-149548 PARSE_SV get_randomize_class_prefix_decl() - Unexpected prefix used with class randomize
AVSREQ-135367 LP_1801 add warning when tool doesn't implement retention on element in set_retention
AVSREQ-146137 VHDL_PERFORMANCE Long elaboration time for chip level design
AVSREQ-139520 SPECMAN_TEMPORAL var value kept across TCM invocations in compiled code
AVSREQ-149297 LP_1801 Update required for packed MDAs for isolation upf_generic_output elements.
AVSREQ-149837 VPI_PLI fsdb runtime crash error code -120 (VPI part)
AVSREQ-143032 PROFILER_MEM_XPROF xmsim crash with profiler (-mem_xprof)
AVSREQ-142994 CORE_SV_IN Need a way to demote BSLLTV to a warning
AVSREQ-144516 PARSE_SV xmvlog_cg INTERR:
AVSREQ-148053 PARSE_PERF xmvlog takes over 1500 sec for a ixcom generated file
AVSREQ-147194 LP_1801 ILLPGP message should be a soft error
AVSREQ-146321 GLS_TIMING Why NTC static delayed values still used despites -nospecify -notimingcheck?
AVSREQ-91048 PARSE_SV INTERNAL EXCEPTION: ivia_rpackage_deference
AVSREQ-146950 PARSE_SV xmvlog: *E,BADSTR unterminated string error with \\ right before ending double quotes
AVSREQ-146691 PARSE_SV xmvlog: *E,DUPIMP & xmvlog: *W,DUPIDNW
AVSREQ-144138 LP_1801 Isolation insertion with -lps_net_split
AVSREQ-138032 SV_GENERAL *E, REFPNSU: $readmemh/$readmemb is currently not supported for ref ports
AVSREQ-142253 SIMVISION_MS Simvision hangs using browse current form and runs to the next statement command
AVSREQ-119964 ELAB_BIND 6) CUVHNF - bind to module.instance.hierarchy not allowed
AVSREQ-145441 SPECMAN_UVM_E uvm e vr_ad : add abs_addr to temp registers created for messaging
AVSREQ-137695 LP_1801 Not able to connect inout logic supply ports to UPF supply net using VCT
AVSREQ-148129 SPECMAN_E Specman Data Browser crash when Custom Numeric Types are used in 64 bit mode
AVSREQ-145196 SIM_FORCE_RELEASE Unexpected force/release behavior in the design
AVSREQ-144900 RAND_SOLVER Assertion error *E when running with 21.03
AVSREQ-142512 LP_1801 Incorrect CNDNRE error message for connect_logic_net where net is only used in power_states
AVSREQ-141100 SIM_SV xcelium simulation with vpi code fails on: xmsim: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-86273 MSIE_ELAB xmelab: *F,INTERR: INTERNAL EXCEPTION MESSAGE: Incelab: Unsupported gate kind in cuv_dv_pconnections
AVSREQ-113171 SYSC_GENERAL Shell not created and compiled by -scautoshell option
AVSREQ-148691 LP_1801 Add error for multiple occurences of -clamp_value in set_isolation
AVSREQ-147859 PROFILER_XPROF xprof crash when merging CPU profile databases - Could not find instance parent for assertion block with id
AVSREQ-148015 JUPITER_BRIDGE Elaboration gets stuck at stage "NACC analysis" after setting "ACC_MULTIDRIVEN_REG=1"
AVSREQ-155786 PARSE_SV xmsim *F,INTERR using $stacktrace
AVSREQ-150210 LP_1801 restore_condition corrupts normal behavior
AVSREQ-145358 LP_1801 Check in multiple enable signals in set_isolation to agile
AVSREQ-116622 SV_GENERAL xmvlog: SOWUNS, "with" expression in streaming concatenation is not supported.
AVSREQ-97715 DMS_ELAB Need EEnet to Real and EEnet to Logic CM support
AVSREQ-147354 DMS_ELAB Allow xm_mirror to support mixed bus i.e generate a warning for mixed buses and skip xm_mirror processing for unsupported types
AVSREQ-140011 RAND_DEBUG OC message should print state variables array values
AVSREQ-151876 XRUN_GENERAL In Sandbox mode used with autofetch the logs show incorrect path of the files
AVSREQ-141482 SIMVISION_GENERAL Simvision .svcf load extremely slow on live simulation
AVSREQ-147030 PARSE_SV $bits not overriding parameters
AVSREQ-142555 DMS_MSIE xmvlog_cg INTERNAL EXCEPTION MESSAGE: gq_datatype_write_net - VST_T_REAL/!QPC_REAL
AVSREQ-142044 XPROPAGATION_GENERAL Incorrect disable messages (XPUIPS) with array corruption
AVSREQ-134957 SV_PERFORMANCE Enhance heap reporting to provide additional reference information
AVSREQ-136043 LP_SIM_PERF Signal from cell not driven correctly upstream with -nolibcellaccess
AVSREQ-149459 FUNC_SAFETY_SIM The result of XFS Serial fault machine is different in 20.09.s008 and 21.03.a001.
AVSREQ-143368 DMS_ELAB Testcase crashes when VHDL-AMS electrical vector connects Verilog
AVSREQ-146421 JUPITER_GL_SC Xcelium MultiCore internal error
AVSREQ-151901 SV_CLASSES Elaboration error 'CLSNPO' : to provide the correct file name and line number as debug information regarding the wrong class
AVSREQ-144870 ELAB_SV Consolidated EHF e141 DPI function not available
AVSREQ-146740 GLS_SDF Tool crash when -sdf_simtime is run along with the switch -ntc_level 3
AVSREQ-146017 JUPITER_BRIDGE Signal abort during linker in DSS flow
AVSREQ-125914 VPI_GENERAL xmsim crash
AVSREQ-130967 ASSERTION_SVA $rose inside disable iff must have a clocking event
AVSREQ-146424 DMS_MSIE Enhance AMSXPT extend explanation from xmhelp to include -msie_resolve_amsxpf
AVSREQ-149389 ELAB_PERF elab slowdown when compiling with -gpg option
AVSREQ-146785 DMS_PERF dms_auto_svrnm_perf is not skipping digital_island checkpoints
AVSREQ-148703 LP_1801 create a unique soft error when xrio isolation reference does not exist in RTL
AVSREQ-91902 PARSE_PERF linear increment in `include statements has a non-linear impact on parser performance
AVSREQ-147927 LP_1801 Elaboration error cannot create and/or open low power file: error creating lib_cell_type_db
AVSREQ-148304 DMS_LP_AMS Elab Crash: Message: finalize_driven_vlog_net - pib/vp null
AVSREQ-147599 SPECMAN_OTHER_LANGUAGES List fields size should be checked when passed from e to C via FLI
AVSREQ-147321 GLS_SDF without SDF runs fine, with SDF its hanging during starting of compilation
AVSREQ-98109 XRUN_GENERAL irun: *E,OPTP2ND: The plus option (+incdir) requires an argument => need to be more specific for debugging in Big SoC VE
AVSREQ-147237 DMS_ELAB Improve the error message for TYCMPAT
AVSREQ-104874 DMS_ELAB Allow connection of multi-dimensional array or vector to electrical port
AVSREQ-114396 SIM_PERFORMANCE Add message if VTW file is not created with -genvtwfile option
AVSREQ-146599 DMS_LP_AMS LP-MS: Analog voltage present in child block, but UPF STATE UNDETERMINED
AVSREQ-142754 LP_1801 Seg fault during lwd_from_snapshot
AVSREQ-139298 SIM_PERFORMANCE Cont assign case-2
AVSREQ-144287 LP_1801 Support for isolation UPF_GENERIC_OUTPUT
AVSREQ-150546 SV_CODEGEN Code generation crash. gq_base_containts_sideeffect: input is not IPS
AVSREQ-119656 SV_DYNAMIC_DATATYPES The -memdetail generate negative number for the heap report
AVSREQ-151993 ELAB_SV Internal Exception during elaboration likely involving use of process::self()
AVSREQ-152200 ELAB_BIND xmelab: *E,CUVUNF hierarchical name lookup failed (using bind construct)
AVSREQ-147861 ELAB_BIND relax_svbmuf has a limit of 10 libraries with the target module
AVSREQ-147486 FUNC_SAFETY b2b runs 1 more simulation than required
AVSREQ-150628 SIM_SV Xcelium crashes when running with randomization debugger
AVSREQ-140521 UVM_ML SIGSEGV inside simulator?
AVSREQ-153098 FUNC_SAFETY_CONCURRENT Different result in Serial and Concurrent when using 21.06.a001.
AVSREQ-116564 SV_PERFORMANCE Improve performance with instance name based name formation
CCRID Product Title
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AVSREQ-140392 ASSERTION_SVA $sampled in disable iff
AVSREQ-148672 PROFILER_MEM_XPROF xmsim crash while using -mem_xprof
AVSREQ-149670 XPROPAGATION_GENERAL cg crash when enabling xprop + enable_var_opt_core
AVSREQ-152734 CORE_RAND Recent librnc causing crash with customer scenario
AVSREQ-147920 SIM_PERFORMANCE xmelab *F,INTERR: INTERNAL EXCEPTION tl_elwait_count_expr - bad expr 850 VST_E_UNKNOWN
AVSREQ-151170 SIM_TCL deposit -scope does not return a correct execution status and does break the -execute in stop command
AVSREQ-130926 PROFILER_SIM_RUNTIME Another concern with PBSR and -profile
AVSREQ-92758 PARSE_SV xmvlog: *EXPRLC and EXPSMC with constructs using inside construct
AVSREQ-146222 ELAB_VHDL VHDL generic map from generic slice to default "others" not properly executed
AVSREQ-149015 ASSERTION_SIM assertoff does not accept ":" as scope name
AVSREQ-149584 COVERAGE_ALL_COVERAGES IMC is crashing when it is unable to load coverage database - sev 0 customer can't reproduce - Ext high
AVSREQ-143124 SV_INTERFACE XMELAB crash pointing to Message cu_vifc_find_master_always
AVSREQ-143462 LP_1801 Support key: for isolation_power_net in query_isolation
AVSREQ-115609 VHDL_PARSE xmvhdl_p generates large number of EXPEND error messages for an extra "," in port map of VHDL
AVSREQ-103591 SPECMAN_COV WARN_UNGRADABLE_ITEM using instance_ranges
AVSREQ-138150 SPECTRE_AMSD SOC level PA RTL AMS sims giving "unable to resolve power supply" error with DVS CM
AVSREQ-149618 RAND_SOLVER Solver using stale value generated by a function call inside constraint block
AVSREQ-107079 ASSERTION_SVF $past usage outside of assertion
AVSREQ-141056 JUPITER_BRIDGE High egress time in customer design when cells contains regs, and -xminitialize is used
AVSREQ-145617 GLS_GENERAL xmelab: *F,INTERR: INTERNAL EXCEPTION - cgtm_evalcc - missed the stream
AVSREQ-100644 DMS_ELAB Signal which has no driver is toggling in AMS simulations
AVSREQ-135711 SIM_PERFORMANCE assignments to vector variable split across generate scopes does not keep correct values
AVSREQ-141738 ASSERTION_SVA xmsim: *E,ASRTST: Assertion failure ($sampled in disable iff)
AVSREQ-148321 PARSE_SV Wrong SVRFDR error when using Resolution Function.
AVSREQ-133339 DMS_AXUM Issue with probe to analog content with SystemVerilog bind to SPICE in Mixed Signal Simulation
AVSREQ-147191 JUPITER_BRIDGE runtime assertion in src/simulator/recipe_execution.inl:2912
AVSREQ-136681 GLS_SDF GLS simulation with SDF of interconnect delay behavior abnormal
AVSREQ-130296 SIMVISION_GENERAL 'Load Signal' waveform option fails when group name has a square bracket
AVSREQ-136932 SIM_SV memory load of a slice with a default value doesnt work
AVSREQ-119271 ASSERTION_SIM Simulation taking huge time with large number of range in SVA assertion
AVSREQ-146780 COVERAGE_FUNCTIONAL $signed in coverpoint is blowing up bin count.
AVSREQ-127428 SV_DPI Issue with compiled cpp on CentOS7
AVSREQ-149528 SIM_PERFORMANCE Verilog memory write data corrupted with -enable_nba_opt perf option
AVSREQ-150437 SIM_TCL [Xcelium] "release" doesn't work with "force -release 50ns object_name = value" setting.
AVSREQ-152046 LP_TCL Values of the keys - isolation_power_net/isolation_ground_net of query_isolation command is incorrect
AVSREQ-146162 SV_CLASSES xmsim crash for function call in constraints
AVSREQ-151371 ELAB_SV During elaboration, xmelab INTERR (vxt_subvst default 652)
AVSREQ-138661 SPECMAN_COV using per_instance in cover group affects item gradeability
AVSREQ-147241 PARSE_SV XCELIUM xmdc INTERNAL EXCEPTION
AVSREQ-148101 ELAB_SV Elaboration crash due to UVM code - xcu_docsp_uniquification - found duplicate class specs for class uvm_sequencer_param_base
AVSREQ-144540 SIM_SV_VHDL Not able to force VHDL port/signal from verilog variable. VHDL side remains U
AVSREQ-153060 ELAB_BIND Elaboration fails to resolve parameter from CU scope
AVSREQ-129662 SIM_SV after time reset, signal on language boundary is set to 'U'
AVSREQ-126255 XPROPAGATION_GENERAL X-Propagation Disabled for Procedures in VHDL
AVSREQ-146978 GLS_PERFORMANCE timing check violation only with "SHM_RESET_DEFAULTS 1"
AVSREQ-149406 RAND_GENERAL Modifying rand_mode on struct arrays has no effect in Xcelium constraint solver
AVSREQ-135499 SIM_CONGRUENCY Congruency support in Dual Snapshot ( MSIE )
AVSREQ-145150 SIMVISION_GENERAL Safety Debug View - multiple selections are confusing users
AVSREQ-103597 DMS_ELAB xmsim crash ssl_trdrv_valuep - odd method
AVSREQ-145782 LP_1801 Query commands execute twice instead of once.
AVSREQ-150599 GLS_GENERAL [Feature req.] Generate a list of signals when the wire leaves X if the time at X exceeds a certain length of time.
AVSREQ-144097 JUPITER_BRIDGE Improve naccing of instances inside compressor and decompressor in ATPG TB
AVSREQ-146993 DMS_SIM Simulation crash when using the stop -at_resfunc debug tcl command
AVSREQ-134870 DMS_LP_AMS LP MS CUNSIF soft error not generated for CM on power domain boundary
AVSREQ-149591 LP_1801 Improve performance of find_objects
AVSREQ-151698 LP_1801 Elaboration crash when using iso_hybrid option
AVSREQ-137393 SV_PARAMETERS xmelab crashed due to genvar variable name
AVSREQ-141036 ELAB_SV The xmelab warning 'BIGWBS' not showing correct instance
AVSREQ-141775 SIM_SV 32-bit simulator behaves differently compared to the 64-bit version
AVSREQ-145286 ELAB_CLONE Elaboration crash with xmclone flow and SystemC uncauterized
AVSREQ-134799 ASSERTION_SIM Simulation performance huge degradation with assertion
AVSREQ-145532 DMS_ELAB xmelab: *E,CUFGPM :: loop generate construct support in +force_ms
AVSREQ-149474 SPECMAN_E Load crash with numeric type field under sys
AVSREQ-143628 XPROPAGATION_GENERAL xprop disabled with localparam used for reset value
AVSREQ-135703 ELAB_SV_VHDL Allow binding to interface inside the bbconnect module
AVSREQ-143578 PARSE_SV SVFWET - unsupported forward declaration of enum type (-enable_fwd_enum and -enable_use_before_decl_in_class)
AVSREQ-151861 LP_1801 DUPGCN error happens in 21.06-a001
AVSREQ-148087 SIM_SV xmsim crash when using the SimVision Simulation Cycle Debugger.
AVSREQ-148819 FUNC_SAFETY_XFSG The equivalent fault is different in SA0 and SA1.
AVSREQ-149816 ELAB_PERF elab memory overhead when parameters are stored in pib
AVSREQ-139047 CORE_RAND Random checkers=2 causes internal errors
AVSREQ-157718 LP_1801 *E,DUPGCN: [LPS] PG pin (VDDC) of cell instance was previously connected to a supply net at this new connection request can not be established
AVSREQ-144984 PARSE_SV SVNT2S error with new -enable_wire_type_param option
AVSREQ-140224 MSIE_ELAB MESSAGE: sv_seghandler - trapno -1 addr((nil))
AVSREQ-145793 FUNC_SAFETY_CONCURRENT XCELIUM21.04_e139 crashed in Concurrent FI
AVSREQ-151643 XRUN_GENERAL Parallel makelib-endlib compile mode causing xrun tool crash:"exec_makelib_parallel_append_log cant open log file"
AVSREQ-152041 GLS_PERFORMANCE GLS simulations runtime performance issue
AVSREQ-141778 SIM_SV Unexpected behavior with "value -keys" tcl command
AVSREQ-132974 GLS_PERFORMANCE xmelab -ntc_level 3 wallclock is 2.5x to 3x compared to without
AVSREQ-141027 PARSE_SV Xcelium always consider *.gz file is a zip file even it is normal .v file
AVSREQ-148389 MSIE_ELAB autohref generation flow misses some cross partition OOMR cases
AVSREQ-112201 PARSE_SV Please support `wrealXState and `wrealZState as legal values for System Verilog Parameters
AVSREQ-146748 FUNC_SAFETY_CONCURRENT CDN_FAULT_CLKTREE caused many "DD" faults to "DU"
AVSREQ-147540 LP_1801 Don't retain time variables
AVSREQ-138845 DMS_AXUM Cannot bind on spice using smos10hv technology : Recursive subcircuit call loop found
AVSREQ-150057 DMS_ELAB Elaboration crashed with -rnm_tech and -wreal wreal1driver
AVSREQ-108717 SIMVISION_DB_UTIL 2087010 CCR SimVision abort when trying to export
AVSREQ-93925 ASSERTION_SVA $sampled fails in disable iff clause of assertion
AVSREQ-150810 SV_PERFORMANCE verilog tasks cause poor performance than competitor
AVSREQ-123952 LP_1801 Inout type power port of PA model causes power net corruption
AVSREQ-147651 DEBUG_DESIGN_DATABASE Indago schematic fails to trace VHDL signal connection over multiple libraries
AVSREQ-110047 MSIE_SIMULATION Signal not driven correctly after deposit from the HDL
AVSREQ-144249 SV_PERFORMANCE newperf opt switch -enable_alcomb_sens_lsp_opt causes Specman DUT error
AVSREQ-132053 SV_PORTS SystemVerilog macro model issue (Logic to Real) in Xcelium
AVSREQ-153896 SIM_PERFORMANCE Using -lwd_complete resulting in core dump
AVSREQ-148138 PARSE_SV Simulation crashed after calling system task $stacktrace
AVSREQ-124288 LP_1801 location information of Isolation needed in "lps_verbose".
AVSREQ-125532 GLS_GENERAL Xcelium VPI Incorrect Value Returned Issue
AVSREQ-146771 XRUN_SYSC xmsc library not found when using -L./../.. notation
AVSREQ-142442 SPECMAN_COMPILE e file translation lingers
AVSREQ-145681 RAND_SOLVER New solver ignores condition in inline dist constraint
AVSREQ-147953 GLS_GENERAL MUX output is getting corrupted when both deposits around inputs to the MUX and the internal node of the mux cell are probed.
AVSREQ-138020 GLS_GENERAL Setup1 :: Elab crash when -afile is used
AVSREQ-148994 JUPITER_BRIDGE JUPITER | MSIE | Fix large time being taken in computing checksum for modules having large number of oomrs in MSIE mode
AVSREQ-121259 ASSERTION_SIM assignment of a property local variable fails
AVSREQ-147424 LP_1801 ISOCUNS Unsupported language construct detected for isolation
AVSREQ-137777 LP_1801 Convert xmlib2cdb execs to comply with all AVS tools
AVSREQ-121381 MSIE_ELAB DSSVAR Error in multi-xrun incremental elaboration
AVSREQ-145772 SIM_SV xmsim INTERR: sv_seghandler - trapno -1 addr(0x8cdbe3) Task run_phase (filee: file_name, line: line_no, in pkg_name)
AVSREQ-125106 SV_DYNAMIC_DATATYPES *E,WOUPXR An expression with queue datatype is not allowed
AVSREQ-144641 GLS_TIMING TC violation when -enable_ntc3_perf is added
AVSREQ-149485 COVERAGE_ALL_COVERAGES libucis core dump
AVSREQ-144061 SPECMAN_COV Coverage UCIS API: support for no_collect coveritems
AVSREQ-142574 VPI_GENERAL $writememh is currently not supported for ref ports
AVSREQ-145206 MSIE_ELAB Possible bug causing elaboration failure while analyzing MSIE partitioning with no error message
AVSREQ-133006 ELAB_PERF irun taking 6+ hours on ixcom generated snapshot for CPU design
AVSREQ-132983 GLS_GENERAL Elaboration Internal error
AVSREQ-91941 XPROPAGATION_GENERAL XPWDIS and XPATT message confusing to users
AVSREQ-141457 SIM_MLTYPEMAP mltypemap enhancement
AVSREQ-143701 LP_1801 Support for the key primary_power_net in query_isolation
AVSREQ-143705 LP_1801 Support for key retention_power_net in query_retention
AVSREQ-149828 CORE_SV_IN xmsim Internal Crash After Indago TCL Re-Elaboration
AVSREQ-141927 XRUN_GENERAL -gdbelab with -symbols use xmelab executable and not xmelab_sym
AVSREQ-123011 SYSC_GENERAL Inconsistent behavior with sc_buffer
AVSREQ-147394 LP_1801 Don't retain time, realtime, wreal, electrical, and string variables
AVSREQ-151753 ELAB_SV xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-115377 PARSE_SV NAMOOL error in Gate Level simulation
AVSREQ-148927 JUPITER_GLST XMSIM crashes after enabling waveform
AVSREQ-144281 LP_1801 Query should return full hierarchical path on isolation keys primary_power_net and isolation_power_net
AVSREQ-144908 SV_PARAMETERS Mixed signal simulation crashes with MESSAGE vst_is_forgen_parameter - unexpected vst kind 'VST_D_OOMR'
AVSREQ-147735 MSIE_ELAB generated externs.sv file name is getting cut-off after 64 chars
AVSREQ-100062 ASSERTION_SVA SVA: Unable to use $sampled in a disable iff clause
AVSREQ-156315 SPECMAN_DEBUG print_stack_trace() prints wrong stack
AVSREQ-148351 VPI_GENERAL NORELO error occurs when using uvm_hdl_release.
AVSREQ-121213 ASSERTION_SIM Assertion failure in simulation does not make sense
AVSREQ-133056 SV_GENERAL streaming operator - unpacking array of structs
AVSREQ-143465 LP_1801 Support for query_pg_info_cell
AVSREQ-153596 ELAB_SV INTERR: NO ERROR for error code 0
AVSREQ-146212 ASSERTION_SIM Getting False Assertion Failures
AVSREQ-147085 SV_GENERAL ILLFMT error when using %p insind $write
AVSREQ-121059 DBG_TRANSRECORD_SDI_VERILOG UVM transactions wrongly rendered in Simvision
AVSREQ-150540 RAND_GENERAL xmsim *F, INTERR with vst_get_source_marker() when using seed_trace
AVSREQ-149225 SIMVISION_MS Lost analog signals from Unified Database convert to vcd format
AVSREQ-120985 DMS_LICENSE The option licinfo doesn't provide DMSO root cause
AVSREQ-146820 SIM_SV Dumping memory in data only format
AVSREQ-152409 ELAB_CLONE Variable on LHS of always_ff not getting updated
AVSREQ-143467 LP_1801 Support for query_supply_net
AVSREQ-152216 DEBUG_DESIGN_DATABASE Indago loads files incorrectly for persistent_sources_debug switch and autofetch used together
AVSREQ-131268 LP_1801 User-defined states coverage defined in add_power_state
AVSREQ-143564 JUPITER_BRIDGE linker failed with error from "native_runtime.cpp" in DSS mode
AVSREQ-146584 ELAB_PERF Large elab times (12 hours) in non timing gate builds
AVSREQ-147235 COVERAGE_CODE Fatal internal error reported when expression coverage is enabled
AVSREQ-134819 ELAB_SV Xcelium 20.09 crashes, 20.03 hangs after elab and 18.09 runs fine with the same design database
AVSREQ-152212 DMS_ELAB INTERNAL Exception error while elaboration ::DR traverse too much times
AVSREQ-140536 LP_1801 [Implementation] Support hard macro - Phase 1
AVSREQ-99091 SV_GENERAL Cryptic UNSRFA compiler error when struct members selected in field automation macro
AVSREQ-138416 DMS_PERF Reduce time spent in vsto_is_constain_spice_oomr_ref
AVSREQ-142492 IP_PROTECT_GENERAL Encryption error 'DECERR'
AVSREQ-122990 XRUN_MULTI_CORE xrun continuing with xmsim despite failing xmelab/mcebuild
AVSREQ-142003 SIM_USABILITY E,NCMCMP in tb migration
AVSREQ-142917 SPECMAN_COMPILE Invalid pointer encountered by GC at load phase
AVSREQ-118260 ELAB_SV xmelab: *E,MULAXX : always_ff : Signal initialization in declaration considered as driver
AVSREQ-150211 RAND_DEBUG Need a way to display failing portion of constraint on SAT timeout
AVSREQ-144946 COVERAGE_GENERAL tool crash with 20.09.009 passes with 19.09.010
AVSREQ-140768 LP_1801 ASRTST error due to assertion control not applied
AVSREQ-144727 LP_1801 Feature Request to add support in xcelium to get ISO_INPUT & ISO_OUTPUT in a generic way
AVSREQ-147381 RAND_SOLVER F.INTERR: INTERNAL EXCEPTION in randomization
AVSREQ-150616 SIM_USABILITY No EndError tag is reported for error with option -enable_msg_marker on xrun: *E, VLGERR
AVSREQ-92962 SIM_SV Support for mailbox as a class type parameter
AVSREQ-148359 JUPITER_BRIDGE JUP_GL_EVAL : Elaboration crash as MCGFE failed in this ATPG case, degradation with Apr Agile release
AVSREQ-92720 SIM_SV Add support for mailbox as class type parameter
AVSREQ-109445 FUNC_SAFETY_SIM Incorrect fault injection time and saif recording time with checkpoints
AVSREQ-141337 LP_1801 Report unsupported UPF commands in a file
AVSREQ-85035 SIM_USABILITY xm_mirror slices of packed array
AVSREQ-102576 PROFILER_SIM_RUNTIME Support -profile argument with PBSR for core digital (and mixed signal) simulation
AVSREQ-152347 SIM_PERFORMANCE FATAL crash on elaboration vst_elem_datatype () - invalid class, class 748
AVSREQ-149085 PARSE_SV Xcelium crashed when invoking tcl stop command
AVSREQ-147751 LP_1801 *N,FOOESR, The find_objects command returns no objects
AVSREQ-144776 SIM_PERFORMANCE Simulation mismatch caused by gprune optimization
AVSREQ-139295 SIM_PERFORMANCE Cont assign case-1
AVSREQ-144105 FUNC_SAFETY_CONCURRENT Memory leakage w/ BADEL in XCELIUM21.01_e981_lnx86_GPLV3_N20210115143022211688
AVSREQ-144771 LP_1801 feedthrough wire is not propagating upf_always_on declared reg value
AVSREQ-149621 DEBUG_DESIGN_DATABASE xmelab with -createdebugdb/-lwdgen resulted in significant increase in size of LWD (3x normal snapshot)
AVSREQ-145297 ASSERTION_PERFORMANCE Slow performance on assertion -off -on
AVSREQ-147886 SV_PARAMETERS INTERR dt_get_known_datatype hit unknown datatype with local type param
AVSREQ-145825 ASSERTION_PERFORMANCE Xcelium get poor performance if there's until in assertion property
AVSREQ-148230 LP_1801 create a unique message when assertion in CAC does not exist
AVSREQ-146372 SIM_USABILITY E,NCMCST in TB migration
AVSREQ-150244 ELAB_SV xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-138458 ELAB_SV To change BNDWRN message for supported items
AVSREQ-92427 PARSE_SV ref event.triggered value is wrong
AVSREQ-138221 SV_DPI Support for longint one dimensional unpacked array type in DPI export function
AVSREQ-146277 SV_GENERAL xmsim crash ( MESSAGE: Anonymous continuous assignment )
AVSREQ-146506 XRUN_GENERAL xrun triggers MKLIBR tag when trying to create a directory
AVSREQ-149935 PARSE_SV Fatal error when enabling coverage
AVSREQ-122504 LP_1801 ERROR:The 'input' pin 'DFT_SPARE[2]' defined for cell 'x' in library 'xx' is either not defined or defined with different direction in the cell 'x' in library 'xxx'
AVSREQ-140975 SV_PERFORMANCE xmsim INTERR : Parallel block sub-process
AVSREQ-144151 JUPITER_GLST Build time degradation in customer design
AVSREQ-142364 LP_1801 [LPS: -lps_net_split] Why these samples are different?
AVSREQ-155251 DMS_LP_AMS INTERR at elab for LP setup
AVSREQ-143975 FUNC_SAFETY_HIER_EXPORT Wrong name extracted during design hierarchy extraction
AVSREQ-87626 PARSE_SV Request to make EXPRLC error a warning for easier migrations
AVSREQ-140219 ELAB_PERF Override parameter value at simulation time
AVSREQ-145195 MSIE_ELAB While doing primary elaboration we get xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-146595 SIM_SV xmelab pmp/dmp sanity failure with debug kit shared for AVSREQ-142277
AVSREQ-144784 SPECTRE_AMSD ams_flex PBSR cold restart failed with spectre terminated prematurely due to fatal error
AVSREQ-111427 SV_PERFORMANCE XMSIM : 2X CPU degradation with -memopt
AVSREQ-146413 SIM_SV Simulation got *F, INTERR if not use linedebug
AVSREQ-147950 XPROPAGATION_GENERAL misleading warning message for enabling XPROP for array corruption
AVSREQ-146007 PARSE_SV xmvlog: *F, INTERR with message vst_root () - no if_ptoroot
AVSREQ-100177 SIMVISION_DB_UTIL Various issues with simvisdbutil
AVSREQ-149177 GLS_TIMING Need to understand NTC topology reported
AVSREQ-115558 PARSE_SV xmelab: *E,TYCMPAT and *E CVMTMM
AVSREQ-151980 SV_INTERFACE xmsim crash - pwrEnableShutOff
AVSREQ-146291 UVM_ML UVM_ERROR using set_propagate_mode with UVM_ML
AVSREQ-140682 SPECMAN_TEMPORAL sn 20.09 fails to initialize integer variable to zero in compiled mode for a while loop
AVSREQ-137109 SV_GENERAL Set membership with array as range
AVSREQ-145205 MSIE_ELAB *E,OPUNSE error not showing up in user's logs
AVSREQ-103472 SV_DPI E,UNUSAG - passing unpacked struct with members that are a packed array of enums to export DPI function.
AVSREQ-138742 FUNC_SAFETY_ELAB XFS20.09/20.11 crashed with -fault_beta option
AVSREQ-153169 ELAB_PERF getting xmelab internal exception when using -newperf
AVSREQ-142846 VHDL_PARSE Error when compiling a modified VHDL STD library
AVSREQ-145300 VPI_GENERAL xcelium internal error: sv_seghandler trapno -1 addr ((nil))
AVSREQ-145099 PARSE_SV Associative array using reg: xmvlog: *E,SVEXTK
AVSREQ-141285 SIM_SV_VHDL Signal propagation difference between xcelium 20.03.002 (and earlier) and 20.09.001 (and later)
AVSREQ-99450 SIM_SV Support of exponential form in atoreal() function
AVSREQ-150043 SIM_PERFORMANCE xmelab INTERR in design that build with older version of xcelium
AVSREQ-148452 RAND_GENERAL Behavior of function in random constraint
AVSREQ-99782 VHDL_GENERAL Support for VHDL 2008 LRM feature "alias hierarchical reference"
AVSREQ-137110 SV_GENERAL E,MEM4 error information insufficient
AVSREQ-145008 ELAB_SV xmelab: *E,BNDBERR - Bit-select index is out of declared bounds
AVSREQ-143135 HAL Hal hang issue
AVSREQ-142448 LP_1801 (PICHON) Elaboration crashed with UPF
AVSREQ-118414 ASSERTION_SIM Support for string variable used in $asserton
AVSREQ-144145 SV_CODEGEN Tool throws internal error during code generation
AVSREQ-147221 SYSC_GENERAL -scautoshell does not work with -makelib
AVSREQ-98617 SV_PERFORMANCE Low Power simulation performance is slow
AVSREQ-103446 SPECMAN_COV Effect of item option "per_instance" on Gradability
AVSREQ-118332 DMS_ELAB xrun restart cannot find verilogA compilation directory
AVSREQ-146159 JUPITER_BRIDGE Xcelium multi-core crash tch_pib1_filter
AVSREQ-149168 GLS_PERFORMANCE GLS+SDF elaboration taking ~26hrs
AVSREQ-134205 ASSERTION_SVA Can -ABV_LRMCOMPLIANT_ASRTCTRL be made default?
AVSREQ-142096 ELAB_SV xmelab crash due to dpes optimization
AVSREQ-152391 DMS_ANALOG_ELAB xmsim internal exception error
AVSREQ-150897 GLS_SDF CPU performance alignment for SDF compilation
AVSREQ-150693 IP_PROTECT_GENERAL DECERR occur when using 21.05.a001
AVSREQ-144024 LP_1801 Support for Information Model propriety LIB_CELL_TYPE
AVSREQ-145029 RAND_SOLVER std:randomize() with two variables produces results which are incorrect (constraints for difference between them are ignored)
AVSREQ-129186 PARSE_SV xmvlog: *E,NULLEI error due to dos format file
AVSREQ-143250 PARSE_SV xmvlog INTERR : dtv_equivalent_type_chk () - invalid class 882
AVSREQ-87366 PROFILER_SIM_RUNTIME How to profile saved or restored simulation using the latest process based save
AVSREQ-142429 SIM_PERFORMANCE Simulator crash on simulation run phase
AVSREQ-143978 SIM_PERFORMANCE LP Simulation fails with -enable_psc_opt and -enable_deadcode_refopt
AVSREQ-73339 PARSE_SV 2094875 CCR ref event.triggered value is wrong
AVSREQ-121869 MSIE_ELAB DSSVAR error in multi-step MSIE flow
AVSREQ-139783 SIMVISION_GENERAL -replace_path in SimVision?
AVSREQ-146110 LP_1801 Elaboration crash in Low Power environment for subelem_chain_next -cannot descend to datatype
AVSREQ-147407 SV_PARAMETERS Incorrectly receiving error "xmelab: *E,NDPIFP: Defparam may not affect the range of an interface IO port."
AVSREQ-147300 XRUN_GENERAL Recompile when switch used twice
AVSREQ-100233 ASSERTION_SVA $sampled in disable iff
AVSREQ-140860 COVERAGE_CODE Expression in function not fully covered
AVSREQ-142888 SV_DATATYPES APSCNS - add support for assignment pattern in bind
AVSREQ-137077 COVERAGE_CODE xcelium treats $bits function differently in coverage mode
AVSREQ-149993 GLS_PERFORMANCE MTRANTO warning and error depending on condition.
AVSREQ-154481 ELAB_SV Xcelium is not returning correct paths to Indago, hence Indago is not able to find the source files
AVSREQ-138189 SV_GENERAL PCRFUP for associative array in ref port
AVSREQ-142413 PARSE_SV INTERR with propfile_vlog source_debug
AVSREQ-149516 DMS_LP_AMS Reduce LPX overhead on customer design
AVSREQ-138351 SV_DPI xmvlog: *E,UNUSAG Error while xcelium migration
AVSREQ-145039 SIM_PERFORMANCE Consolidated EHF e194 test fails with -enable_var_opt_core
AVSREQ-141620 DMS_WREAL Tool crashed during xmvlog_cg
AVSREQ-150800 GLS_PERFORMANCE Elaboration time improvement for in-house customer design
AVSREQ-138977 LP_1801 Supress all messages (error, warning, notes) that are not related to low power
AVSREQ-146447 DMS_LP_AMS LP MS: Bidirectional Switch with wrealavg resolution is not calculating correct voltage
AVSREQ-141242 DMS_AXUM Issue with probe to analog content with SystemVerilog bind to SPICE in Mixed Signal Simulation
AVSREQ-106973 SV_GENERAL $inferred_clock system task used
AVSREQ-144598 SIMVISION_CONSOLE SimVision console is stuck while searching with the text box
AVSREQ-145204 PARSE_SV *F,INTERR: INTERNAL EXCEPTION -if_modify_structure - New type (651) is larger than the old type (565)
AVSREQ-148737 SR_BACKDOOR Probable memory leak in solver in CX mode
AVSREQ-139758 PARSE_SV xmelab TYCMPAT error with parameterized modules and $bits usage
AVSREQ-149405 LP_1801 query_isolation support for hybrid isolation information
AVSREQ-93134 ELAB_CLONE xmelab: *E,INCUSC: Unsupported port connection type (unsupported expression on actual) identified
AVSREQ-147089 IP_PROTECT_GENERAL Encryption causes NULLEI errors
AVSREQ-144817 GLS_PERFORMANCE "-enctran" degradation since 21.01
AVSREQ-125269 LP_1801 xmelab: *E,MULSPLY: [LPS] Multiple UPF supply (testbench.rtd_vbat.VBAT42_UPF, testbench.rtd_vbat.VS
AVSREQ-139065 PARSE_SV xmvlog: *EXPRLC and EXPSMC with constructs using inside construct
AVSREQ-151057 ELAB_PERF Design elab crash
AVSREQ-100445 PARSE_SV "side" .pak creation using ncvlog and System Verilog RTL
AVSREQ-148550 LP_1801 Why the xmlib2cdb generate the "line -1" for duplicated cell case?
AVSREQ-86945 PROFILER_SIM_RUNTIME -profile doesn't work with -process_save
AVSREQ-145481 JUPITER_COMPILER support xminitialize rand and rand_2state modes in multi-core
AVSREQ-144428 SV_INTERFACE xmelab crash on function cu_vifc_check_access with 21.03.g286Debug kit
AVSREQ-152296 ELAB_SV During elaboration, xmelab INTERR (NO ERROR for error code 0)
AVSREQ-141505 XRUN_GENERAL -xmlibdirname is not expanding $ variable in below scripting form
AVSREQ-121979 XPROPAGATION_GENERAL XPROP making signal X without cause, works with access C
AVSREQ-101035 DMS_ANALOG_ELAB DVS doesn't report error even if invalid vddnet/vssnet is provided
AVSREQ-146534 PROFILER_SIM_MEMORY Allow memdetail (or similar) to be a runtime switch
AVSREQ-142516 LP_1801 Commenting out a connect_logic_net unexpectedly causes a port to go z'
AVSREQ-150740 LP_1801 set_port_attribute does not work on unconnected ports
AVSREQ-141733 LP_VHDL Enhance request for LP VHDL report
AVSREQ-135088 DMS_AXUM Undefined model found by analog solver because of sv binding definition
AVSREQ-144676 DEBUG_PROBE SST2ER: SST2 interface error: Series sort buffer maximum size reached
AVSREQ-152677 MSIE_ELAB AutoMSIE : OPPNSE error with OOPR to enum.method call
AVSREQ-148817 RAND_SOLVER Support start/end delimiters for multiline *W,*E,*F,*N messages in Randomization code
AVSREQ-148146 SIM_PERFORMANCE $deposit not triggering waveform or downstream update
AVSREQ-145701 ELAB_SV Elaboration failure due to name clash between parameter override (-gpg) and enum element
AVSREQ-123677 ELAB_SV Relaxation for NONOWD error with -xlm_bq1 -vlogrelax only for first occurrence
AVSREQ-148843 SV_PARAMETERS xmelab crashing with MESSAGE: sv_seghandler - trapno -1 addr((nil))
AVSREQ-143321 LP_1801 Enable the change of AVSREQ-138931 with a switch
AVSREQ-100902 ASSERTION_DEBUG total failed assertion count
AVSREQ-144188 SPECMAN_E Invalid pointer encountered by GC at runtime
AVSREQ-142603 LP_1801 Support for UPF_ROOT_SUPPLY
AVSREQ-144177 DMS_ANALOG_ELAB AMS analog signal becomes zero at certain hierarchy level
AVSREQ-149813 ELAB_PERF elab is 10x slower with -access r and no -access option in customer design
JIRA ID COMPONENT SUMMARY
AVSREQ-145942 SPECMAN_COV Specman does not error for non-existence of cover group kind
AVSREQ-147725 MSIE_PERFORMANCE Multi-xrun simulation perf - global module pessimism
AVSREQ-144440 DMS_ASSERTIONS FVCADCDN-4619 : Xcelium_Option:- Testcase getting crash with xcelium option -show_rnm_cover at elaboration phase.
AVSREQ-134354 LP_CPF [PA RTL] Use of -lps_reg_mfile causes elaboration to quit skipping the final snapshot creation, causing simulation failure
AVSREQ-147065 DMS_ELAB xmelab INTERR: sv_seghandler - SIGSEGV while handling SIGSEGV
AVSREQ-148266 GLS_GENERAL different simulation behavior when VCD format waves dump
AVSREQ-101389 ESW_SYMBOLICDEBUG Display of union type with bit field is incorrect in Indago ESWD
AVSREQ-148174 ASSERTION_DEBUG asrctl message in one line
AVSREQ-142291 DEBUG_DESIGN_DATABASE Wrong signal name representation in waveform window on packed struct member select
AVSREQ-142534 LP_1801 LP-NORTELE error occurrence at Xmelab
AVSREQ-148086 ASSERTION_PERFORMANCE Migration: Assertion performance enhancement is needed to improve CPS gap
AVSREQ-148036 CORE_SV_IN default perf switch da_two_stated_mem_opt causing test fail
AVSREQ-140004 JUPITER_COMPILER South crash due to a circle created by power gaters optimizations
AVSREQ-145868 SV_GENERAL Migration: bit repetition fails in ternary expression with streaming concatenation
AVSREQ-147664 LP_1801 Log file enhancement for sim2clp with -lps_net_split
AVSREQ-99433 SIMVISION_DB_UTIL Simvision abort when trying to export - full fix
AVSREQ-139389 FUNC_SAFETY_ELAB Internal exception error during elaboration with "-fault_beta" option
AVSREQ-138896 DMS_AXUM bind on spice automatically impossible with vcfg_no_default_bind
AVSREQ-88717 ELAB_SV Add option to allow initializations as one of two drivers (for FPGA synthesis).
AVSREQ-138780 SV_PERFORMANCE improve performance for big testbench bottleneck
AVSREQ-145971 LP_CPF Iso control condition maintained while condition is inactive
AVSREQ-142614 XPROPAGATION_GENERAL xprop report with systemC TB generates a wrong report
AVSREQ-119259 DMS_LP_AMS Two supply nets in UPF scope are connecting to the same HDL(wreal) signal results in xmelab: *E,CSNMCN
AVSREQ-152257 SV_GENERAL wrong sign expansion and operation
AVSREQ-130278 PROFILER_XPROF Iprof should plot run time and memory vs wall clock time
AVSREQ-152088 DEBUG_DESIGN_DATABASE Indago source browser showing values in one instance only (other instances missing)
AVSREQ-153320 SV_PERFORMANCE *F, INTERR, sv_seghandler with -enable_cb_ddce
AVSREQ-147195 LP_1801 xrio should be updated with additional switches for interface support
AVSREQ-93324 SIM_SV SVTPOU error when using mailbox in uvm_config_db
AVSREQ-152156 PROFILER_SIM_RUNTIME Enhance the reporting of memdetail for MEM_DETAIL_REPORT_LIMIT
AVSREQ-151375 GLS_SDF sdf_ignore_simvhdl does not fix SDFSVIT
AVSREQ-140968 SIM_FORCE_RELEASE "force" assignments do not happen in the generate "for" loop with xrun
AVSREQ-151686 SIM_PERFORMANCE *F, INTERR, sv_seghandler
AVSREQ-152171 MSIE_ELAB add support of OOPR for mixed-language design
AVSREQ-151116 DMS_BIND Request to downgrade EXANCU error to a warning if -dms_fast_debug option is enabled
AVSREQ-143120 SV_PERFORMANCE Xcelium skips task line unless nearby $display or -linedebug
AVSREQ-143348 DMS_ANALOG_ELAB Unexpected OBANOVL 'object does not exist' error for nets
AVSREQ-141348 SV_ALL atoreal removing - sign when ^M is at the end of the number
AVSREQ-144661 PROFILER_SIM_RUNTIME xmprofmerge profile data doesn't match the actual profile data
AVSREQ-147630 IP_PROTECT_GENERAL xmprotect results in encryption that you cannot browse waveforms even with -simulation debugall with certain compiler directive/macros defined.
AVSREQ-136402 MSIE_ELAB MESSAGE: sv_seghandler - trapno -1 addr((nil))
AVSREQ-148054 COVERAGE_PERFORMANCE xmelab taking ~5 hours on ixcom generated model
AVSREQ-145001 FUNC_SAFETY_CONCURRENT Support always @(*) having more than one unpacked memory in reference
AVSREQ-151084 DMS_AXUM *E,AMSMDA error for multi dimensional array to spice connection
AVSREQ-144391 FUNC_SAFETY_CONCURRENT fault is DU in serial and UU in concurrent
AVSREQ-130551 ELAB_BIND Limit the scope of warnings
AVSREQ-150095 ASSERTION_PERFORMANCE always_comb gives wrong results when using structs
AVSREQ-132671 ELAB_SV BNDWRN - Message enhancement to show instance hierarchical path, array size and bit select range
AVSREQ-139932 SV_GENERAL CUVNPM error when $bits() is used with hier path in a SV bind context
AVSREQ-119751 SYSC_GENERAL scautoshell does not support modules not compiled into the worklib
AVSREQ-147885 PARSE_SV incorrect invalid type error
AVSREQ-121385 SIM_CAPTURE_REPLAY Insert fixed delay on specified signals during replay
AVSREQ-146096 LP_1801 Support for upf_generic_pre_iso
AVSREQ-131604 LP_1801 support all assertion control in liberty model through create_assertion_control -lib_model {*}
AVSREQ-76588 SIM_SV mailbox as class type param
AVSREQ-143086 SV_GENERAL BSCXSZ Error
AVSREQ-146772 SIMVISION_MS Need equivalent TCL command for Browse Currents
AVSREQ-112202 PARSE_SV Please support `wrealXState and `wrealZState as legal values for System Verilog Struct - real member initializer
AVSREQ-150359 DMS_LP_AMS WUDNPFS for set_port_attribute reference on an intermediary port
AVSREQ-133383 SV_GENERAL E,ILLPRI Error at customer end
AVSREQ-149756 ELAB_SV Tool crash with message vst_immediate_scope() - bad class
AVSREQ-152106 DMS_BIND INTERR in check_is_svvhdl_mixoomr_and_resolve
AVSREQ-150865 DEBUG_DESIGN_DATABASE Indago does not load and hangs on the Cadence logo on some farm machines
AVSREQ-147318 PARSE_SV Improve xmvlog MACRDF warning message to include prior define location
AVSREQ-143977 SIM_USABILITY Xmsim : Message: sv_seghandler: dynamic out-of-bounds wait on an expanded wire
AVSREQ-148935 SV_CODEGEN Large enum.next() handling is too slow
AVSREQ-125551 DMS_WREAL *F, INTERR with message "gq_vload_defval - not a vector"
AVSREQ-139515 SIM_PERFORMANCE xmelab INTERR: Always pruned, but register did not qualify
AVSREQ-105580 SV_GENERAL Support for 'with' expression in streaming concatenation, xmvlog: *E,SOWUNS
AVSREQ-148353 COVERAGE_SIMULATION Different simulations results with coverage.
AVSREQ-108688 XPROPAGATION_GENERAL remove XPWDIS message in xp_elab where -xverbose exists
AVSREQ-146516 GLS_GENERAL IOPATH timing altering with and without VCD dumping
AVSREQ-138429 SV_DPI UNSUAF error with DPI-C error and shortreal
AVSREQ-133926 ASSERTION_SVA xmvlog: *E,SFLNOS (SFLNOS.sv,12|53): SystemVerilog streaming concatenation operator in this context is not supported.
AVSREQ-152685 ELAB_SV xmelab INTERR: NO ERROR for error code 0
AVSREQ-145471 LP_1801 bind_checker.sv is not created if added -lps_cov.
AVSREQ-141240 LP_1801 balloon style register is not corrupt when retention supply becomes corrupt + Retention enable signal is not being corrupted when toggling during CORRUPT_ON_ACTIVITY
AVSREQ-141160 SIM_CAPTURE_REPLAY Enhance XMREPLAY_SIGNAL_REPLAY_FILE to support inversed value replay
AVSREQ-152376 GLS_PERFORMANCE "-suptran" option requires "-access +w" to be applied.
AVSREQ-147816 SV_INTERFACE CUIMBC ELAB ERROR related to 3rd party VIP
AVSREQ-147688 RAND_GENERAL No VALFIT warning for nested class constraints
AVSREQ-120369 SV_PORTS Support event argument to a module
AVSREQ-138708 PARSE_SV xmvlog should be able to handle dos characters in source files
AVSREQ-100135 SV_GENERAL default port value support
AVSREQ-148040 GLS_GENERAL xmsim crashes with the message SSS_MT_FRZ_BYTE
AVSREQ-145055 SV_GENERAL lwdgen causes elab to hang
AVSREQ-148365 JUPITER_BRIDGE JUP_pATPG_DSS : 35x degradation in incremental elaboration, nacc_analysis stage exploding and taking 23hrs
AVSREQ-144401 SIM_PERFORMANCE Optimizing latch where registers with different bits are shared in different latches
AVSREQ-132293 SIM_PERFORMANCE Always latch not being pruned
AVSREQ-145395 SPECTRE_AMSD Two xcelium.d directories get created when -xmlibdirname argument is used with FLEX
AVSREQ-145989 GLS_GENERAL Build crash with 21.03-a001 debug kit
AVSREQ-145487 MSIE_ELAB Another -nolog issue with MSIE
AVSREQ-111251 ELAB_SV xmelab *E,QDANBA error.
AVSREQ-147384 PARSE_PERF Performance degradation with -librescan option
AVSREQ-149078 SPECMAN_E Bad enum value for 'numeric_format_kind' when printing numeric type with radix setting
AVSREQ-149000 COVERAGE_CODE simulator hangs with coverage enabled
AVSREQ-148734 SPECTRE_AMSD Name a digital event by the event index: digital changes for CCR2488607
AVSREQ-145936 GLS_GENERAL simulator different behavior 20.09.007 -> 20.09.010
AVSREQ-152694 XPROPAGATION_GENERAL *F,INTERR: INTERNAL EXCEPTION is coming out with using the xprop -c
AVSREQ-138451 SV_BUILD_PERF elab consistently slows down, memprof attached
AVSREQ-147295 PARSE_SV Positional parameters handled incorrectly for local type param
AVSREQ-143690 SV_DPI DPI issue while using SvBitVecValue in C functions
AVSREQ-148293 IP_PROTECT_GENERAL Xcelium report error when perform "memory -load" with a memory in protected IP
AVSREQ-147293 SV_GENERAL FJNRFA not reported on function resolved through type param
AVSREQ-147926 LP_1801 Crash due upf_get_value_str call for a LIB_CELL_TYPE handle
AVSREQ-137306 XRUN_GENERAL xrun -timescale -compile should flag a warning
AVSREQ-144390 LP_1801 [PUNIT] LPS - streaming concat breaking functionality
AVSREQ-151755 ELAB_SV During elaboration, xmelab INTERR (ivia_pair_sanity_check - vst and ot mismatch for vst class)
AVSREQ-145235 SPECMAN_UVM_E uvm e vr_ad : update( ) call from write_reg_raw() changes the direction to be WRITE inappropriately
AVSREQ-143461 LP_1801 Support for the key: location in query_isolation
AVSREQ-102428 DMS_ELAB EEnet package should take of EEnet nettype as logic and wrealsum (custom)
AVSREQ-145660 VPI_PLI AMS co-simulation crash with fatal error SIGUSR Unix Signal SIGSEGV with specman interface
AVSREQ-143237 SV_PORTS Elab enable read access of ref port variables in $writememb/$writememh
AVSREQ-136946 SPECTRE_AMSD Simulation failure due to VHDL Alias usage in MS context
AVSREQ-146685 RAND_DEBUG Constraint debugger does not take to the correct TLP bucket where the variable is solved
AVSREQ-150443 SPECMAN_E C FLI mapping of uint(bits:33-64) into C uint64_t
AVSREQ-148102 SIM_SV_VHDL wrong OOMR assign value to record when field initiated with function
AVSREQ-144673 LP_1801 To track CCMPR02459003 (another issue found in UPF-linter in case apply_power_model inside power model)
AVSREQ-105449 SV_GENERAL Support for bitstream operator in assignment to dynamic array
AVSREQ-151331 LP_VPI LWD failure on customer LP design
AVSREQ-92651 SIM_SV ncvlog: *E,SVTPCO (): Currently type parameter override is not supported for this datatype.
AVSREQ-105058 SV_GENERAL Xcelium stream operation does not support "with"
AVSREQ-149433 LP_1801 Power model with supply state and logic expression in add_power_state corrupts VSSE pin
AVSREQ-144285 LP_1801 Query should return primary_power_net key based on isolation location.
AVSREQ-157734 ELAB_BIND Xcelium elaboration fails with xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-128927 PARSE_SV support for module name exceeding 1023 characters
AVSREQ-136024 PARSE_SV Option to downgrade PMBNOB error to a warning
AVSREQ-144778 SIM_SV xmsim INTERR: svvi_get_stream - stream not found
AVSREQ-138352 DMS_ELAB add more support to dms_report option
AVSREQ-73650 SV_PORTS Fatal Error when using -primtop
AVSREQ-105392 SV_GENERAL Xcelium stream operation does not support "with"
AVSREQ-152079 ELAB_CLONE xmclone: *E,INCUSC for {OOMR, enum-literal} in port expression
AVSREQ-144997 XRUN_MSIE elaboration crash with autoreplicated_top
AVSREQ-132598 COVERAGE_CODE Enhancement request to support code coverage on expressions involving "inside" construct
AVSREQ-101568 SV_GENERAL Module port default values not working
AVSREQ-152904 FUNC_SAFETY_ELAB XFS is crashing at elab time with -fault_rtl switch
AVSREQ-133691 JUPITER_HVIEW MC_EVAL_BUILD_PERF: 1.4X elaboration memory overhead with mce_hview
AVSREQ-147494 PROFILER_SIM_MEMORY memory profiler doesnt show memory allocated at c using chandle
AVSREQ-137764 SIMVISION_WAVEFORMS loading to simvision svwf with changes breaks
AVSREQ-140105 SV_INTERFACE abnormal shm signal value dump in Dynamic Test + LP sim
AVSREQ-144855 MSIE_ELAB [MSIE] xmelab: *E,IEPKGF: Package not shared between partitions. [solved]
AVSREQ-136045 VHDL_PARSE SIGPUP (Signal expressions on unconstrained port) error
AVSREQ-143549 CORE_RAND Solver crashes with the new Xcelium solver, Solves successfully in legacy solver
AVSREQ-139633 PARSE_SV ILLGVR, This genvar cannot be used in this context
AVSREQ-153271 SIM_USABILITY No EndError EndWarning reported with option -enable_msg_marker with xmvlog
AVSREQ-135874 LP_1801 support of apply_power_model inside a power model is missing
AVSREQ-151738 DEBUG_DESIGN_DATABASE Indago exits unexpectedly with a memory error during interactive debugging
AVSREQ-155345 SIM_PERFORMANCE Internal exception during elaboration with 21.03.v005
AVSREQ-153292 SIM_CAPTURE_REPLAY 'XMReplay' spell wall warning : agile/xcelium
AVSREQ-145685 SIM_PERFORMANCE Xcelium RTL compile – stack trace while using 21.02-a001
AVSREQ-137643 SIM_TCL Enabling thread support in TCL + bundle TCL Thread Extension package in our installation
AVSREQ-138565 DMS_ELAB dms_report file is not getting generated withtout rnm_coerce and disres switch
AVSREQ-151225 SIM_PERFORMANCE Simulation hang at time zero with newperf switch enable_alcomb_ext_opt
AVSREQ-126254 XPROPAGATION_GENERAL X-Propagation Disabled for Call to procedure in VHDL
AVSREQ-140203 JUPITER_RTL_SC MC build crash while MC split
AVSREQ-146875 CORE_RAND Randomization engine producing incorrect values due to issues with function calls
AVSREQ-119262 LP_1801 p/nwells connected to supply nets/ports vdd_24v/gnd_24v not getting the voltage
AVSREQ-153068 SPECMAN_E Internal Assertion triggered when using TLM ports with templates of value parameters and hex radix
AVSREQ-141106 COVERAGE_SIMULATION Throw an error for using optimize_dump in ccf
AVSREQ-152329 SIM_SV Wrong behavior of sting concatenation operator
AVSREQ-147218 SV_GENERAL CLSSVN when using non blocking event triger
AVSREQ-111637 SIM_PERFORMANCE VTW not converting intf signals, cont assignments appearing in xmprof
AVSREQ-141094 SPECMAN_METHODOLOGY vr_ad_mem alloc - assumes size is int
AVSREQ-142590 LP_1801 Support for upf_query_pg_info(hdl_path, "", UPF_PRIMARY_POWER_PGTYPE)
AVSREQ-121380 SIM_CAPTURE_REPLAY Replay specified signals after inverting them
AVSREQ-149866 SPECMAN_COMPILE Internal Error when creating elib with sn_compile.sh
AVSREQ-146112 PARSE_SV Enhancement req. about stream op. with ternary op.
AVSREQ-145973 PROFILER_XPROF ".xmprof_summary.out" mismatches the gui result of xprof.
AVSREQ-138526 LP_SV Low power probing incorrectly creates probes inside of protected region
AVSREQ-151272 RAND_DEBUG Can't see array values when using an index
AVSREQ-126152 FUNC_SAFETY_CONCURRENT performance issue with concurrent engine on a given campaign
AVSREQ-134375 LP_1801 Support for set_port_attribute reference to create_logic_port signal
AVSREQ-136977 HAL not queuing the license properly
AVSREQ-135996 SV_DYNAMIC_DATATYPES [XLM] difference behavior between alloate dynamic array in or out function
AVSREQ-149203 SPECTRE_AMSD Blackbox with dspf does not work in AMS
AVSREQ-148390 SIM_SV After reset command the always block not executing
AVSREQ-144466 DEBUG_PROBE Using ida_probe -start_time=<current time> returns an error
AVSREQ-145071 ELAB_CLONE xmclone crash with 20.03 due to $deposit in replicated hierarchy
AVSREQ-144942 SV_BUILD_PERF xmelab slowdown issue
AVSREQ-131200 LP_1801 Question about SNDRMU warning and elaboration perf issue
AVSREQ-152464 SPECMAN_SAVE_RESTORE Indago launch crash (OS signal 11) at Specman 'DA restore'
AVSREQ-153398 SV_PERF The simulation behavior is different between w/wo -newperf
AVSREQ-147783 LP_1801 associate_supply_set FSpec and implementation
AVSREQ-139422 GLS_GENERAL Support for deposit -sense_input option in $xm_deposit
AVSREQ-138688 LP_1801 1821128: xmlib2cdb creates error when interface_timing used with function
AVSREQ-156909 GLS_SDF xmsim INTERNAL EXCEPTION MESSAGE: rts_net_fse - bad stopreason (0)
AVSREQ-91358 SV_DATATYPES APSCNS - add support for assignment pattern in bind
AVSREQ-151196 ASSERTION_SVA W,ACTBDN warning changed to *E, SCPAUR when add -enable_abv_asrtctrl_enh
AVSREQ-144319 ELAB_VHDL Support generic override, -gpg, for vhdl type unsigned
AVSREQ-147505 ELAB_SV Getting DLNORD error on second run of single-step MSIE elaboration
AVSREQ-134488 LP_1801 UPFERRM is triggered when argument of -type use curly braces
AVSREQ-140122 RAND_SOLVER rts_abrthandler - SIGABRT unexpected violation pc=0x2b671bbda4f5 addr=0x7340aef900017a7a
AVSREQ-150132 SV_PARAMETERS xmelab: *F,INTERR dto_range_width - no width
AVSREQ-149351 SV_PERFORMANCE Xcelium performance is slower than competitor
AVSREQ-147736 GLS_PERFORMANCE Huge Simulation time in GLS.
AVSREQ-142469 LP_1801 *F,INTERR: INTERNAL EXCEPTION when elaboration with UPF
AVSREQ-149518 DMS_LP_AMS Reduce LPX overhead on customer design with DMS
AVSREQ-140669 SIM_USABILITY Issue with $deposit command
AVSREQ-125273 ASSERTION_SVF xmvlog: *E,SELPRV : Use of variable or variable-index in the select expression inside the sampled value function $changed is not supported.
AVSREQ-143466 LP_1801 Support for query_cell_mapped
AVSREQ-141215 PARSE_SV Erroneous xmvlog: *E,ILLHIN (final.sv,34|153): illegal location for a hierarchical name (in a package) only when using parameterized type
AVSREQ-150839 PARSE_SV xmvlog INTERR:: get_randomize_class_prefix_decl() - Unexpected prefix used with class randomize
AVSREQ-147382 IXCOM How to use VDMs for the latest VIPCAT
AVSREQ-145188 XRUN_MULTI_CORE Add xmhelp xrun entry for MCE2CON
AVSREQ-143579 CORE_RAND RNDREFA - unsupported scope randomization of ref arg
AVSREQ-145854 DMS_LP_AMS LP MS: incorrect VOLTAGE values for bidirectional switch model with wrealavg
AVSREQ-150939 GLS_GENERAL functional difference if the UDP output is probed or not
AVSREQ-149823 PARSE_SV Please improve PANOTL error
AVSREQ-146496 XPROPAGATION_GENERAL Provide XPROP support with case expression width > 64 bits
AVSREQ-147495 SIM_SV Simulation is stuck at sort() SV function
AVSREQ-144246 SIM_PERFORMANCE *E,BDOPT on newperf opt switch -enable_varca_stream_opt
AVSREQ-150042 DMS_ELAB Elaboration crash with SystemVerilog assertion pointing to vst_expr and cag_get_driving_expr (when using inherited connections mixed signal algorithm)
AVSREQ-149705 SIM_VHPI need support for VHPI to work in uVisa mode with OTs
AVSREQ-143469 LP_1801 lps_time0_isox glitch
AVSREQ-140148 ASSERTION_SVA Unexpected ASRTST message
AVSREQ-152851 DMS_LP_AMS internal exception when UPF function find_objects is applied on SV-RNM User Defined Nettype
AVSREQ-145761 DMS_LP_AMS CPF shutoff condition with electrical expression shows *E,WCNDINO
AVSREQ-102479 SIM_SV_VHDL Request OOMR write support for VHDL record and record elements
AVSREQ-138966 SIM_SV Demote $error - *E, ERRSEV to have an exit status '0'
AVSREQ-99128 LP_1801 extend lps_cov to cover also add_power_state
AVSREQ-148399 SPECMAN_COV Cadence/XCELIUM/21.02.001- Running Specman testbench faulier
AVSREQ-119882 PARSE_SV unused library in cds.lib gets unnecessary pak file created
AVSREQ-139447 SIM_VHDL failing to describe memory
AVSREQ-149619 VPI_PLI VPI Internal error on uvm_hdl_force
AVSREQ-142762 UVM_ML_OA_INSTALL SPECMAN_DLIB should no longer be dumped into setup.* when building UVM-ML-OA
AVSREQ-145030 PARSE_PERF sv bind consumes memory 10 times.
AVSREQ-150001 LP_1801 set_design_attributes -elements <element_list> UPF_dont_touch not honored
AVSREQ-142970 JUPITER_COMPILER *F,MCEASRT: Multi-core elaboration assertion 'An expanded template signal 'N' of width '5' has wrong number of template vars
AVSREQ-144445 XRUN_GENERAL fast_recompilation prevents elaboration from re-elaborating
AVSREQ-152326 JUPITER_ENGINE wave dump optimisation for optimized out egress
AVSREQ-145852 PARSE_SV INTERR dt_is_array hit unknown datatype (VST_T_TYPE_PARAMETER)
AVSREQ-129214 ASSERTION_SIM Several false failures of an assertion during simulation
AVSREQ-134608 XRUN_GENERAL single quotes added to SPECMAN_PATH prevents Specman restore
AVSREQ-132953 GLS_GENERAL unexpected behavior of verilog primitive
AVSREQ-151634 SV_GENERAL GLS simulation crash when running with -ENTCHGROUP
AVSREQ-143502 LP_1801 Automatic lib2cdb conversion tries to write to read-only directory
AVSREQ-151711 XPROPAGATION_GENERAL Provide debug information with side-effect methods
AVSREQ-147605 SV_CODEGEN Simulation differences in +access+rw vs afile runs. -disableopt leads to code generation crash
AVSREQ-140804 SAVE_RESTART_DMTCP Segmentation fault on user code when restoring on a machine with different arch
AVSREQ-143119 SV_PERFORMANCE Xcelium Optimization Bug - line of task ignored without a $display() or -linedebug
AVSREQ-145622 JUPITER_BRIDGE CAG is causing more HardEgress when run with "-access +r"
AVSREQ-146177 DMS_AMSD *E, AFHDWT (…) Elaboration error with analog_node_alias()
AVSREQ-147387 FUNC_SAFETY fs_strobe parsing issue: signal defined as a checker strobe is listed as a functional strobe in FLDT detection message
AVSREQ-146081 DEBUG_DESIGN_DATABASE Indago becomes unresponsive
AVSREQ-146489 SIM_TCL 'deposit -scope' command fails when called from a sourced TCL script
AVSREQ-150404 GLS_TIMING sv_seghandler - trapno -1 addr(0x1fc)
AVSREQ-149815 SIM_USABILITY xmsim: *E,OBJACC: Object must have read access: <…signal name…>
AVSREQ-119397 ELAB_SV xmelab: *W,CUVIHR :: when reference is made to generate item present inside interface
AVSREQ-148387 RAND_SOLVER Unexpected randomization result
AVSREQ-151308 SPECMAN_DEBUG OS signal 11 using Specman debugger
AVSREQ-148187 VWDB to support auto-update
AVSREQ-138989 DMS_WREAL xmelab internal error when coverage enabled: rts_abrthandler - SIGABRT unexpected violation
AVSREQ-140729 DMS_LP_AMS support vct mapping for wrealZState to UPF net
AVSREQ-146529 SIM_USABILITY Create an identifying tag to indicate if warning and error messages span multiple lines
AVSREQ-142616 PARSE_SV import DPI inside of a generated if statement causes compile error
AVSREQ-115112 PARSE_SV xmelab: *E,CUVUNF (adapter.sv,554|20): Hierarchical name component lookup failed for 'resp' at 'nitro_axi_pkg'
AVSREQ-141204 ASSERTION_DEBUG internal error while changing assertion via assertion tcl cmd
AVSREQ-155368 SIM_PERFORMANCE INTERNAL EXCEPTION during elaboration
AVSREQ-147228 SV_PORTS xmelab: *E, PCIONC - Expression connected to an 'inout' port must be collapsible.
AVSREQ-147888 PARSE_SV Reported line numbers mismatch for CUVUNF
AVSREQ-151579 JUPITER_COMPILER Override delay mode for specific path in MC
AVSREQ-144607 SV_GENERAL customer migration: macro code for ternary expression , wrong functionality
AVSREQ-136161 XPROPAGATION_GENERAL REGSOV elab error when applying Xfile
AVSREQ-150106 LP_SV xmelab: *E,STRMOP: [LPS] Stream concat operator failure: offset/size incorrect
AVSREQ-143703 LP_1801 Support for the key primary_power_net in query_retention
AVSREQ-141216 VPI_LWD indago takes 4 minutes to open UVM hierarchy
AVSREQ-152643 SPECTRE_AMSD Flex 2.0: block any analog tcl command once users shut down Spectre process via 'exit -analogsolver'
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AVSREQ-144825 UVM_SV uvm command line processor is unable to read command line arguments when XMSIMOPTS environment variable is set
AVSREQ-141776 PARSE_SV Non-printable characters instead of filename in error message
AVSREQ-144342 ELAB_SV xmvlog: *E,NONOWD, Illegal use of a constant without an explicit width specification
AVSREQ-149645 SIMVISION_GENERAL Crash issue in Cross probing between VSE and SimVision
AVSREQ-149808 PARSE_SV generate error message instead of a crash
AVSREQ-141229 PARSE_SV xmvlog INTERR Unexpected Signal #11
AVSREQ-152207 LP_1801 bind_checker doesn't support multiple indexes
AVSREQ-143715 XM_UTILS_GENERAL xmgentb -selfchk does not generate a correct self-checking testbench
AVSREQ-143678 GLS_SDF internal error when using sdf_simtime to annotate sdf in sim time
AVSREQ-143344 SV_GENERAL disable iff assertion fail while it should not
AVSREQ-141655 LP_1801 Isolation cell is not inserted with -lps_net_split
AVSREQ-152414 LP_SV interface inout ports values not updated in UPF simulation
AVSREQ-145501 COVERAGE_FUNCTIONAL Enhance COVLNB warning to include cross/coverpoint count
AVSREQ-116654 SV_GENERAL -vlogcontrolrelax NOTPAR doesn't work
AVSREQ-122334 ELAB_SV xmelab: *E,MULAXX Multiple drivers to always_ff output - with variable declaration initializers
AVSREQ-148162 SIM_PERFORMANCE Elaboration crash in Modem environment for ivia_rpackage_dereference-NULL instance
AVSREQ-119972 SIM_SV inverter output stuck 0 for some time peoriod.
AVSREQ-136379 SIM_USABILITY CUNOBJ information insufficient
AVSREQ-149970 MSIE_SIMULATION Randomisation + MSIE bbox flow - error during simulation
AVSREQ-132889 COVERAGE_TOGGLE packed struct is not showing as completely covered
AVSREQ-151281 ELAB_SV xmelab crash related to vst_immediate_scope() - bad class, class 623
AVSREQ-153278 DMS_ANALOG_ELAB xmsim: *E,SYERROR occurs only when analog object(Verilog-AMS instance) in SV module(with local param)
AVSREQ-134803 SV_GENERAL Initialization of dynamic array not applied on new declaration
AVSREQ-133372 SV_PERFORMANCE xmsim size keeps growing
AVSREQ-149817 ELAB_PERF simulation difference with -gpg_sim when overriding value at simulation
AVSREQ-118629 LP_1801 Same supply net connection in UPF and RTL
AVSREQ-123954 ELAB_SV *W,BNDWRN: Support wire type - bit select out of boundary
AVSREQ-150946 SIM_PERFORMANCE Please print -disableopt individual flags in log and -stdout_option output
AVSREQ-144657 LP_1801 Enhancement on LIBINLIB to automatically connect inside liberty as always_on.
AVSREQ-141442 SIMVISION_MS SimVision: Connect modules are missing in Schematic Tracer
AVSREQ-148690 LP_1801 files generated with "-lps_cov" have compile issues…
AVSREQ-100802 LP_1801 supply net connected to inout in module
AVSREQ-137112 SIM_SV heap report tcl command does not report reference in class tasks
AVSREQ-147240 LP_1801 Supply net GND is not connected to upper level DVSS
AVSREQ-146341 JUPITER_BRIDGE Requesting $countdrivers and $showvars support
AVSREQ-134833 LP_1801 Isolation cell for split net insertion is not expected
AVSREQ-144353 DEBUG_PROBE Using ida_probe -start_time=<current time> returns an error
AVSREQ-150403 ELAB_DOC Question about the description of -caint
AVSREQ-146942 VPI_GENERAL vpiTimePrecision wrong computation
AVSREQ-145326 SPECTRE_AMSD IP Export Reuse flow with xmlibdirpath give ERROR (SFE-868) "nosuchfile.sp"
AVSREQ-153044 ELAB_VHDL xmvhdl_cg internal exception gq_psunlink - missing succ when migrating IXCOM flow to Xcelium 20.09-s013
AVSREQ-151011 SAVE_RESTART_DMTCP Xcelium is crashing on specific CPU platform
AVSREQ-152317 SIM_PERFORMANCE ELAB CPU degradation with super_prune optimization
AVSREQ-154393 ELAB_PERF Xcelium build takes 108GB without -ENABLE_PSC_OPT
AVSREQ-149278 SIM_PERFORMANCE Internal Error (gq_ttold - switch followed by CUVCGF) during xmvlog_cg
AVSREQ-116742 SIM_USABILITY Support -nowarn LDVAL
AVSREQ-148728 SIMVISION_GENERAL E,UNKOPT: unrecognized option for the simvision command (-title)
AVSREQ-145221 SIMVISION_MS Current Browser: Create Probe from Browse Currents fails
AVSREQ-142382 LP_SIM_PERF Xmsim crash at SimTime 0 with ENABLE_PSC_OPT
AVSREQ-96162 DMS_AXUM AXUM: Enable connection of multi-dimensional array or vector to electrical port
AVSREQ-106626 MSIE_ELAB Need of "-congruency" switch in MSIE flow
AVSREQ-139400 SPECMAN_TEMPORAL Wrong behaviour of nested 'all off' and 'all of for' in a TCM
AVSREQ-102437 DMS_ELAB Elaboration error *E,CICAPC
AVSREQ-144889 SV_CODEGEN Intel SoC: tool Fatal on elab
AVSREQ-135432 DMS_ANALOG_ELAB lost analog bus OOMR connection using SV file without port
AVSREQ-153921 DEBUG_DESIGN_DATABASE LWD database enhancements cause regression builds to hang at customer
AVSREQ-151889 LP_1801 The find_objects command returns no objects *N, FOOESR
AVSREQ-141857 DMS_LP_AMS Plans for enhancing interface support for CPF
AVSREQ-146592 ELAB_BIND CUIMBC when trying to implicitly connect interface port to another bound unit
AVSREQ-145126 CORE_RAND Possible bug in multi-pass causing constraint contradiction
AVSREQ-142343 SIM_VHDL Simulation Crash using vhdl_seq_nba but no crash with vhdlsync
AVSREQ-154299 DMS_LP_AMS Elaboration tool crash Design contains WREAL models + CPF.
AVSREQ-148031 COVERAGE_FUNCTIONAL Disabling Functional coverage during compile time
AVSREQ-151870 SIM_PERFORMANCE xmelab *F,INTERR: INTERNAL EXCEPTION tl_elwait_count_expr - bad expr 850 VXT_E_UNKNOWN
AVSREQ-151931 RAND_SOLVER Unexpected randomization results with new tool version.
AVSREQ-151647 DMS_LP_AMS ILOBJUE message created for a signal that exists
AVSREQ-144411 SIM_PERFORMANCE xmelab: *F,INTERR: tl_analyze_pib_usefulness - live pot dftSmsPipeline1_adl maps to dead pib OT with -redinline
AVSREQ-146900 SPECMAN_ERRORS Recursion during signal handling
AVSREQ-144672 ELAB_BIND MSIE with VHDL configs does not work
AVSREQ-153696 DMS_ELAB SIEDTM error using scalar connections(x) to SIE Input port specified as wire [0:0] x
AVSREQ-150367 LP_1801 Elaboration crash for Modem MSS Low Power environment, nettmp_kind -null nettmp
AVSREQ-128086 UVM_ML_SYSC bug in uvm_sc adapter
AVSREQ-81574 COVERAGE_CODE exclude coverage of methods called from pragma coverage off regions
AVSREQ-148416 DMS_LP_AMS WUDNPFS error for no_isolation specification for a coerced net
AVSREQ-137961 SIM_SV probe -screen displays incorrect value for signal which should be XXX under shut off condition
AVSREQ-144143 LP_SV comb. always block is replayed at power-up while it should not
AVSREQ-147338 RAND_GENERAL Randomization crash in MSIE flow
AVSREQ-93548 SIM_SV *E, SVTPOU: Currently type parameter override is not supported for this datatype (mailbox)
AVSREQ-138003 ASSERTION_SIM -enable_var_opt_core causing simulation Error on final immediate assertion
AVSREQ-106456 SV_PERF $sdi_set_attribute_by_name consuming CPU cycles
AVSREQ-146130 SV_PERFORMANCE Clocking Blocks on runtime performance
AVSREQ-144658 LP_1801 Support on VCT table for PARTIAL_ON translation to '1'.
AVSREQ-148480 ASSERTION_SIM assertion takes a lot of memory on sv heap, doesn't seem to clear
AVSREQ-147048 LP_1801 xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-141583 LP_1801 Make option -lps_vhdl_reg_opt default
AVSREQ-93232 ASSERTION_SVA Assertion failures when the disable iff is active at the prepond region
AVSREQ-145380 SIM_USABILITY Elaboration performance degraded with a newer version of agile, 21.02-a(2x)
AVSREQ-148841 JUPITER_BRIDGE JUP_pATPG_DSS: Elaboration crash in incremental. Degradation w/ 21.04-a001.
AVSREQ-118534 SPECTRE_AMSD VoltusFi+AMSD+Xcelium Flow: Support blackbox module in dspf_include - when it is configured to Verilog/HDL
AVSREQ-152444 LP_1801 Retention is not obeying set signal
AVSREQ-143451 VPI_GENERAL ERROR: VPI NOPTVAL vpi_put_value() cannot place a value into the object of type vpiPartSelect.
AVSREQ-134320 ELAB_SV Enhancement to support custom format for elaboration $info messages
AVSREQ-146241 LP_BUILD_PERF XMELAB: LSNDHDL-LPS warning occurrence
AVSREQ-113321 LP_1801 Implementation - UPF supply net & port re-architecture
AVSREQ-142484 GLS_SDF The RETAIN timing arcs are ignored when the SDF annotation is performed dynamically.
AVSREQ-152894 SIM_PERFORMANCE change MEMIND to MEMPC when memopt and IDA/probe is used
AVSREQ-144763 SIM_PERFORMANCE removing -enable_dotstar_var_tlg_assoc from newperf - 21.03.v001
AVSREQ-142277 SIM_SV Xcelium crashes when doing reset from Indago gui
AVSREQ-140031 CORE_SV_IN Systemverilog fork-join statement activation issue (new error scenario)
AVSREQ-130205 FUNC_SAFETY_CONCURRENT 8x+ overhead when using the BADEL optimization
AVSREQ-147395 PARSE_SV fatal error on compilation when using -enable_strict_macroref
AVSREQ-152192 SIM_PERFORMANCE newperf with -disable_alcomb_ext_opt not working effectively
–––––––+––––––––––––––-+––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––+––––––––––––––-+–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
AVSREQ-88954 SV_GENERAL xmvlog: *E,SOWUNS (testit.sv,18|22): with expression in streaming concatenation is not supported
AVSREQ-139054 ELAB_BIND xmelab: *E,CUVUNF - bind to module.instance.hierarchy not allowed
AVSREQ-149548 PARSE_SV get_randomize_class_prefix_decl() - Unexpected prefix used with class randomize
AVSREQ-135367 LP_1801 add warning when tool doesn't implement retention on element in set_retention
AVSREQ-146137 VHDL_PERFORMANCE Long elaboration time for chip level design
AVSREQ-139520 SPECMAN_TEMPORAL var value kept across TCM invocations in compiled code
AVSREQ-149297 LP_1801 Update required for packed MDAs for isolation upf_generic_output elements.
AVSREQ-149837 VPI_PLI fsdb runtime crash error code -120 (VPI part)
AVSREQ-143032 PROFILER_MEM_XPROF xmsim crash with profiler (-mem_xprof)
AVSREQ-142994 CORE_SV_IN Need a way to demote BSLLTV to a warning
AVSREQ-144516 PARSE_SV xmvlog_cg INTERR:
AVSREQ-148053 PARSE_PERF xmvlog takes over 1500 sec for a ixcom generated file
AVSREQ-147194 LP_1801 ILLPGP message should be a soft error
AVSREQ-146321 GLS_TIMING Why NTC static delayed values still used despites -nospecify -notimingcheck?
AVSREQ-91048 PARSE_SV INTERNAL EXCEPTION: ivia_rpackage_deference
AVSREQ-146950 PARSE_SV xmvlog: *E,BADSTR unterminated string error with \\ right before ending double quotes
AVSREQ-146691 PARSE_SV xmvlog: *E,DUPIMP & xmvlog: *W,DUPIDNW
AVSREQ-144138 LP_1801 Isolation insertion with -lps_net_split
AVSREQ-138032 SV_GENERAL *E, REFPNSU: $readmemh/$readmemb is currently not supported for ref ports
AVSREQ-142253 SIMVISION_MS Simvision hangs using browse current form and runs to the next statement command
AVSREQ-119964 ELAB_BIND 6) CUVHNF - bind to module.instance.hierarchy not allowed
AVSREQ-145441 SPECMAN_UVM_E uvm e vr_ad : add abs_addr to temp registers created for messaging
AVSREQ-137695 LP_1801 Not able to connect inout logic supply ports to UPF supply net using VCT
AVSREQ-148129 SPECMAN_E Specman Data Browser crash when Custom Numeric Types are used in 64 bit mode
AVSREQ-145196 SIM_FORCE_RELEASE Unexpected force/release behavior in the design
AVSREQ-144900 RAND_SOLVER Assertion error *E when running with 21.03
AVSREQ-142512 LP_1801 Incorrect CNDNRE error message for connect_logic_net where net is only used in power_states
AVSREQ-141100 SIM_SV xcelium simulation with vpi code fails on: xmsim: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-86273 MSIE_ELAB xmelab: *F,INTERR: INTERNAL EXCEPTION MESSAGE: Incelab: Unsupported gate kind in cuv_dv_pconnections
AVSREQ-113171 SYSC_GENERAL Shell not created and compiled by -scautoshell option
AVSREQ-148691 LP_1801 Add error for multiple occurences of -clamp_value in set_isolation
AVSREQ-147859 PROFILER_XPROF xprof crash when merging CPU profile databases - Could not find instance parent for assertion block with id
AVSREQ-148015 JUPITER_BRIDGE Elaboration gets stuck at stage "NACC analysis" after setting "ACC_MULTIDRIVEN_REG=1"
AVSREQ-155786 PARSE_SV xmsim *F,INTERR using $stacktrace
AVSREQ-150210 LP_1801 restore_condition corrupts normal behavior
AVSREQ-145358 LP_1801 Check in multiple enable signals in set_isolation to agile
AVSREQ-116622 SV_GENERAL xmvlog: SOWUNS, "with" expression in streaming concatenation is not supported.
AVSREQ-97715 DMS_ELAB Need EEnet to Real and EEnet to Logic CM support
AVSREQ-147354 DMS_ELAB Allow xm_mirror to support mixed bus i.e generate a warning for mixed buses and skip xm_mirror processing for unsupported types
AVSREQ-140011 RAND_DEBUG OC message should print state variables array values
AVSREQ-151876 XRUN_GENERAL In Sandbox mode used with autofetch the logs show incorrect path of the files
AVSREQ-141482 SIMVISION_GENERAL Simvision .svcf load extremely slow on live simulation
AVSREQ-147030 PARSE_SV $bits not overriding parameters
AVSREQ-142555 DMS_MSIE xmvlog_cg INTERNAL EXCEPTION MESSAGE: gq_datatype_write_net - VST_T_REAL/!QPC_REAL
AVSREQ-142044 XPROPAGATION_GENERAL Incorrect disable messages (XPUIPS) with array corruption
AVSREQ-134957 SV_PERFORMANCE Enhance heap reporting to provide additional reference information
AVSREQ-136043 LP_SIM_PERF Signal from cell not driven correctly upstream with -nolibcellaccess
AVSREQ-149459 FUNC_SAFETY_SIM The result of XFS Serial fault machine is different in 20.09.s008 and 21.03.a001.
AVSREQ-143368 DMS_ELAB Testcase crashes when VHDL-AMS electrical vector connects Verilog
AVSREQ-146421 JUPITER_GL_SC Xcelium MultiCore internal error
AVSREQ-151901 SV_CLASSES Elaboration error 'CLSNPO' : to provide the correct file name and line number as debug information regarding the wrong class
AVSREQ-144870 ELAB_SV Consolidated EHF e141 DPI function not available
AVSREQ-146740 GLS_SDF Tool crash when -sdf_simtime is run along with the switch -ntc_level 3
AVSREQ-146017 JUPITER_BRIDGE Signal abort during linker in DSS flow
AVSREQ-125914 VPI_GENERAL xmsim crash
AVSREQ-130967 ASSERTION_SVA $rose inside disable iff must have a clocking event
AVSREQ-146424 DMS_MSIE Enhance AMSXPT extend explanation from xmhelp to include -msie_resolve_amsxpf
AVSREQ-149389 ELAB_PERF elab slowdown when compiling with -gpg option
AVSREQ-146785 DMS_PERF dms_auto_svrnm_perf is not skipping digital_island checkpoints
AVSREQ-148703 LP_1801 create a unique soft error when xrio isolation reference does not exist in RTL
AVSREQ-91902 PARSE_PERF linear increment in `include statements has a non-linear impact on parser performance
AVSREQ-147927 LP_1801 Elaboration error cannot create and/or open low power file: error creating lib_cell_type_db
AVSREQ-148304 DMS_LP_AMS Elab Crash: Message: finalize_driven_vlog_net - pib/vp null
AVSREQ-147599 SPECMAN_OTHER_LANGUAGES List fields size should be checked when passed from e to C via FLI
AVSREQ-147321 GLS_SDF without SDF runs fine, with SDF its hanging during starting of compilation
AVSREQ-98109 XRUN_GENERAL irun: *E,OPTP2ND: The plus option (+incdir) requires an argument => need to be more specific for debugging in Big SoC VE
AVSREQ-147237 DMS_ELAB Improve the error message for TYCMPAT
AVSREQ-104874 DMS_ELAB Allow connection of multi-dimensional array or vector to electrical port
AVSREQ-114396 SIM_PERFORMANCE Add message if VTW file is not created with -genvtwfile option
AVSREQ-146599 DMS_LP_AMS LP-MS: Analog voltage present in child block, but UPF STATE UNDETERMINED
AVSREQ-142754 LP_1801 Seg fault during lwd_from_snapshot
AVSREQ-139298 SIM_PERFORMANCE Cont assign case-2
AVSREQ-144287 LP_1801 Support for isolation UPF_GENERIC_OUTPUT
AVSREQ-150546 SV_CODEGEN Code generation crash. gq_base_containts_sideeffect: input is not IPS
AVSREQ-119656 SV_DYNAMIC_DATATYPES The -memdetail generate negative number for the heap report
AVSREQ-151993 ELAB_SV Internal Exception during elaboration likely involving use of process::self()
AVSREQ-152200 ELAB_BIND xmelab: *E,CUVUNF hierarchical name lookup failed (using bind construct)
AVSREQ-147861 ELAB_BIND relax_svbmuf has a limit of 10 libraries with the target module
AVSREQ-147486 FUNC_SAFETY b2b runs 1 more simulation than required
AVSREQ-150628 SIM_SV Xcelium crashes when running with randomization debugger
AVSREQ-140521 UVM_ML SIGSEGV inside simulator?
AVSREQ-153098 FUNC_SAFETY_CONCURRENT Different result in Serial and Concurrent when using 21.06.a001.
AVSREQ-116564 SV_PERFORMANCE Improve performance with instance name based name formation
==============================================
CCRID Product Title
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JIRA ID COMPONENT SUMMARY
AVSREQ-154822 VHDL_PARSE Using an underscore as the first character in library name causes xmvhdl_p: *E,BADLPP error
AVSREQ-155914 DEBUG_PROBE Disable MTD in Interactive mode
AVSREQ-147485 FUNC_SAFETY B2B fails for FS_CHECKPOINT_TYPE=TIME_OPT
AVSREQ-157142 DMS_MSIE xmelab INTERR with MSIE
AVSREQ-154490 IXCOM xmelab *F INTERNAL EXCEPTION sss_hname - can't find AOI index
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AVSREQ-157111 ELAB_SV_VHDL SystemVerilog alias appears unconnected
AVSREQ-155037 DMS_AMSD xmelab CUVNCM error with -cds_implicit_tmpdir and custom SVAMS CM
AVSREQ-155586 DEBUG_PROBE Simulation exits unexpectedly: rts_abrthandler - SIGABRT unexpected violation
AVSREQ-155341 VHDL_PARSE xmvhdl_p * F,INTERR:INTERNAL EXCEPTION
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
JIRA ID COMPONENT SUMMARY
AVSREQ-154822 VHDL_PARSE Using an underscore as the first character in library name causes xmvhdl_p: *E,BADLPP error
AVSREQ-155914 DEBUG_PROBE Disable MTD in Interactive mode
AVSREQ-147485 FUNC_SAFETY B2B fails for FS_CHECKPOINT_TYPE=TIME_OPT
AVSREQ-157142 DMS_MSIE xmelab INTERR with MSIE
AVSREQ-154490 IXCOM xmelab *F INTERNAL EXCEPTION sss_hname - can't find AOI index
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AVSREQ-157111 ELAB_SV_VHDL SystemVerilog alias appears unconnected
AVSREQ-155037 DMS_AMSD xmelab CUVNCM error with -cds_implicit_tmpdir and custom SVAMS CM
AVSREQ-155586 DEBUG_PROBE Simulation exits unexpectedly: rts_abrthandler - SIGABRT unexpected violation
AVSREQ-155341 VHDL_PARSE xmvhdl_p * F,INTERR:INTERNAL EXCEPTION
================================================
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-156115 SIM_SAIF_TCF Forward SAIF usage in dumpsaif TCL command causes xmsim segfault
AVSREQ-157907 SIM_VHDL VHDL code does not behave the same way in 2103 vs 1909
AVSREQ-155741 SIM_SPARSE_ARRAY [degrade] REGSOV error for large size array.
AVSREQ-149203 SPECTRE_AMSD Blackbox with dspf does not work in AMS
AVSREQ-156092 VHDL_PERFORMANCE unexpected memory consumption on mixed language simulation.
AVSREQ-150359 DMS_LP_AMS WUDNPFS for set_port_attribute reference on an intermediary port
AVSREQ-155927 ELAB_PERF '1 interpreted as 1 with -constexpropt
AVSREQ-157408 SIMVISION_DB_UTIL A way to share waveform file at a specific hierarchy (IP level) with hierarchies above the IP level stripped
AVSREQ-155919 SIM_SPARSE_ARRAY Memory Blow up 6.7 Gig to 29 Gig - from 19.01.001 to 21.07.001
JIRA ID COMPONENT SUMMARY
AVSREQ-142993 GLS_GENERAL Xcelium crashed while elaboration.
AVSREQ-77655 GLS_TIMING Warning NTCNNC is not reported with option -ntc_verbose
AVSREQ-118534 SPECTRE_AMSD VoltusFi+AMSD+Xcelium Flow: Support blackbox module in dspf_include - when it is configured to Verilog/HDL
AVSREQ-155445 SIMVISION_DB_UTIL Simvisdbutil: Extracted signal hierarchy is lost while extracting signals present inside struct datatype
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AVSREQ-155057 SIM_USABILITY Support -nowarn LDVAL when provided using XRUNOPTS.
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-156115 SIM_SAIF_TCF Forward SAIF usage in dumpsaif TCL command causes xmsim segfault
AVSREQ-157907 SIM_VHDL VHDL code does not behave the same way in 2103 vs 1909
AVSREQ-155741 SIM_SPARSE_ARRAY [degrade] REGSOV error for large size array.
AVSREQ-149203 SPECTRE_AMSD Blackbox with dspf does not work in AMS
AVSREQ-156092 VHDL_PERFORMANCE unexpected memory consumption on mixed language simulation.
AVSREQ-150359 DMS_LP_AMS WUDNPFS for set_port_attribute reference on an intermediary port
AVSREQ-155927 ELAB_PERF '1 interpreted as 1 with -constexpropt
AVSREQ-157408 SIMVISION_DB_UTIL A way to share waveform file at a specific hierarchy (IP level) with hierarchies above the IP level stripped
AVSREQ-155919 SIM_SPARSE_ARRAY Memory Blow up 6.7 Gig to 29 Gig - from 19.01.001 to 21.07.001
JIRA ID COMPONENT SUMMARY
AVSREQ-142993 GLS_GENERAL Xcelium crashed while elaboration.
AVSREQ-77655 GLS_TIMING Warning NTCNNC is not reported with option -ntc_verbose
AVSREQ-118534 SPECTRE_AMSD VoltusFi+AMSD+Xcelium Flow: Support blackbox module in dspf_include - when it is configured to Verilog/HDL
AVSREQ-155445 SIMVISION_DB_UTIL Simvisdbutil: Extracted signal hierarchy is lost while extracting signals present inside struct datatype
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AVSREQ-155057 SIM_USABILITY Support -nowarn LDVAL when provided using XRUNOPTS.
===================================
CCRID Product Title
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AVSREQ-146758 UVM_SV uvm_hdl_force converts X'es to 1's when target is in VHDL
AVSREQ-151079 DMS_SVAMS INTERR with amsd - on design using SV-UDN and logic connectmodules(DMS IEs)
AVSREQ-160042 GLS_SDF Internal exception: MESSAGE: rts_abrthandler - SIGABRT unexpected violation
AVSREQ-154024 ELAB_PERF 2-4x increase in elaboration time when switching from 19.12a to 20.11a
AVSREQ-155727 DMS_ANALOG_ELAB A "reg" type bus connected to a module gives error
AVSREQ-160084 XRUN_JASPER Remove "-disable_auto_bbox" from default JasperGold UNR flow
AVSREQ-156883 ELAB_PERF Xcelium elab performance degradation in latest versions 21.03
AVSREQ-146770 SIMVISION_MS Provide additional information for Describe command used with mixed net instance
AVSREQ-150489 GLS_TIMING ISOINTI error occur when using 21.03.a001
AVSREQ-82520 DEBUG_PROBE Problem with probing signals exceeding 4096 bits
JIRA ID COMPONENT SUMMARY
AVSREQ-159080 DEBUG_PROBE Memory declared as wires exceeding VWDB limit are ignored but probed by SHM
AVSREQ-154069 LP_1801 Missing isolation when using set_repeater
AVSREQ-152645 SV_GENERAL Internal exception when providing incorrect module names in the toggle exclude file
AVSREQ-125104 DEBUG_PROBE -packed/-unpacked should apply to both wires and variables/regs
AVSREQ-159875 GLS_SDF Xcelium21.09.002 elaboration crash
AVSREQ-157095 VHDL_GENERAL Event on VHDL record does not trigger a wait statement
AVSREQ-158960 LP_1801 associate_supply_set doesn't accept ss in terminal boundary
AVSREQ-157423 GLS_TIMING Xcelium21.03.007 elaboration crash (part1)
AVSREQ-151322 SV_PORTS Elaboration crash with sv_seghandler - trapno -1 addr(0x20)
AVSREQ-157588 IP_PROTECT_GENERAL Customers need Xcelium20.03s released w/ new IPPLIB
AVSREQ-157239 SIMVISION_MS Mixed Net Browser: sort not working for scientific notation values
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-146758 UVM_SV uvm_hdl_force converts X'es to 1's when target is in VHDL
AVSREQ-151079 DMS_SVAMS INTERR with amsd - on design using SV-UDN and logic connectmodules(DMS IEs)
AVSREQ-160042 GLS_SDF Internal exception: MESSAGE: rts_abrthandler - SIGABRT unexpected violation
AVSREQ-154024 ELAB_PERF 2-4x increase in elaboration time when switching from 19.12a to 20.11a
AVSREQ-155727 DMS_ANALOG_ELAB A "reg" type bus connected to a module gives error
AVSREQ-160084 XRUN_JASPER Remove "-disable_auto_bbox" from default JasperGold UNR flow
AVSREQ-156883 ELAB_PERF Xcelium elab performance degradation in latest versions 21.03
AVSREQ-146770 SIMVISION_MS Provide additional information for Describe command used with mixed net instance
AVSREQ-150489 GLS_TIMING ISOINTI error occur when using 21.03.a001
AVSREQ-82520 DEBUG_PROBE Problem with probing signals exceeding 4096 bits
JIRA ID COMPONENT SUMMARY
AVSREQ-159080 DEBUG_PROBE Memory declared as wires exceeding VWDB limit are ignored but probed by SHM
AVSREQ-154069 LP_1801 Missing isolation when using set_repeater
AVSREQ-152645 SV_GENERAL Internal exception when providing incorrect module names in the toggle exclude file
AVSREQ-125104 DEBUG_PROBE -packed/-unpacked should apply to both wires and variables/regs
AVSREQ-159875 GLS_SDF Xcelium21.09.002 elaboration crash
AVSREQ-157095 VHDL_GENERAL Event on VHDL record does not trigger a wait statement
AVSREQ-158960 LP_1801 associate_supply_set doesn't accept ss in terminal boundary
AVSREQ-157423 GLS_TIMING Xcelium21.03.007 elaboration crash (part1)
AVSREQ-151322 SV_PORTS Elaboration crash with sv_seghandler - trapno -1 addr(0x20)
AVSREQ-157588 IP_PROTECT_GENERAL Customers need Xcelium20.03s released w/ new IPPLIB
AVSREQ-157239 SIMVISION_MS Mixed Net Browser: sort not working for scientific notation values
============================================
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-159326 DEBUG_DESIGN_DATABASE modifications to support gpg_sim for vpiStringConst parameters
AVSREQ-154044 SV_PERFORMANCE Task inline optimization causing test failure
AVSREQ-157023 SIM_SV xmsim crash: MESSAGE: T(0): sv_seghandler - trapno -1 addr(0x7fd52ce94a08) Method SSS_MT_SVHASSIGN_ER_US
AVSREQ-158347 SV_GENERAL Simulation mismatch due to failed queue concatenation
AVSREQ-156467 SAVE_RESTART_CHECKPOINT (PBSR) simulation not restarting when both -cds_alternate_dir and -cds_implicit_dir are specified
AVSREQ-161045 LP_1801 Elab fails with *F,INTERR: INTERNAL EXCEPTION error , when ran with Low Power UPF
AVSREQ-160462 VPI_GENERAL rand_2state : n generates wrong results
AVSREQ-159623 XPROPAGATION_GENERAL ELAB crash: gq_maxbitaccess - no bit vector
JIRA ID COMPONENT SUMMARY
AVSREQ-157989 LP_1801 [LPS] Xcelium can't insert isolation cell with -lps_iso_netsplit
AVSREQ-160491 GLS_SDF wor not fulfilled when using annotating INTERCONNECT on connected pad
AVSREQ-155067 LP_1801 What is an expected result of W,ILUOTB and W,ILOBJUE, when setting "-attribute terminal_boundary TRUE" for a set_design_attribute in LPSIM?
–––––––+––––––––––––-+–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––+––––––––––––-+––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
AVSREQ-157798 LP_1801 Got elaboration INTERNAL EXCEPTION after using UPF
AVSREQ-161863 ELAB_PERF Replay Optimizations on 2109 Main
AVSREQ-158402 SIM_PERFORMANCE Mixed packed+unpacked multi-dimensional array transfer from one variable to another not working
AVSREQ-160574 SIMVISION_MS AMSD_Simvision : Schematic Tracer : Signal not connected to port
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-159326 DEBUG_DESIGN_DATABASE modifications to support gpg_sim for vpiStringConst parameters
AVSREQ-154044 SV_PERFORMANCE Task inline optimization causing test failure
AVSREQ-157023 SIM_SV xmsim crash: MESSAGE: T(0): sv_seghandler - trapno -1 addr(0x7fd52ce94a08) Method SSS_MT_SVHASSIGN_ER_US
AVSREQ-158347 SV_GENERAL Simulation mismatch due to failed queue concatenation
AVSREQ-156467 SAVE_RESTART_CHECKPOINT (PBSR) simulation not restarting when both -cds_alternate_dir and -cds_implicit_dir are specified
AVSREQ-161045 LP_1801 Elab fails with *F,INTERR: INTERNAL EXCEPTION error , when ran with Low Power UPF
AVSREQ-160462 VPI_GENERAL rand_2state : n generates wrong results
AVSREQ-159623 XPROPAGATION_GENERAL ELAB crash: gq_maxbitaccess - no bit vector
JIRA ID COMPONENT SUMMARY
AVSREQ-157989 LP_1801 [LPS] Xcelium can't insert isolation cell with -lps_iso_netsplit
AVSREQ-160491 GLS_SDF wor not fulfilled when using annotating INTERCONNECT on connected pad
AVSREQ-155067 LP_1801 What is an expected result of W,ILUOTB and W,ILOBJUE, when setting "-attribute terminal_boundary TRUE" for a set_design_attribute in LPSIM?
–––––––+––––––––––––-+–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––+––––––––––––-+––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
AVSREQ-157798 LP_1801 Got elaboration INTERNAL EXCEPTION after using UPF
AVSREQ-161863 ELAB_PERF Replay Optimizations on 2109 Main
AVSREQ-158402 SIM_PERFORMANCE Mixed packed+unpacked multi-dimensional array transfer from one variable to another not working
AVSREQ-160574 SIMVISION_MS AMSD_Simvision : Schematic Tracer : Signal not connected to port
==================================
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-154625 GLS_TIMING xmsim internal error when selecting DUT in Design Browser
AVSREQ-161421 LP_1801 MESSAGE: vst_name() - invalid class, class 688
AVSREQ-164049 LP_1801 Tool crash during elaboration after adding -lps_power_tchecks
AVSREQ-155766 LP_1801 LPVASRT error is seen during elaboration while dumping the coverage with lps_cov option
AVSREQ-159919 DEBUG_DESIGN_DATABASE Driver Tracing - VHDL signal tracing not working
AVSREQ-161226 ELAB_SV simulation internal error with Xcelium 21.09.003
AVSREQ-152873 GLS_TIMING Xcelium Simulation crash: Anonymous continuous assignment
AVSREQ-163710 LP_1801 xmsim: *E,LPSNORL when -lps_cov is used
AVSREQ-160428 DCP Rename .xmdcp directory to .dcp
AVSREQ-163616 DMS_ELAB xmelab *F INTERNAL EXCEPTION sss_hname - can't find AOI index (looks like AVSREQ-154490)
AVSREQ-164612 SIM_TCL The environment variable $TCLLIBPATH overridden by Xcelium
AVSREQ-150392 LP_1801 Using -lps_cov is resulting in LPOVLG Error
AVSREQ-155534 DMS_LP_AMS Crash during elaboration in SPICE+UPF sim with message: p_pot = NULL [NULL decl POT] - pwr_break_expr_vlog_etc
AVSREQ-163009 ELAB_SV xmsim: *E,RNDERR Randomization has encountered a bug: Internal error.
AVSREQ-157384 IP_PROTECT_GENERAL Xmvlog compile error for encrypted file
JIRA ID COMPONENT SUMMARY
AVSREQ-164447 SIMVISION_MS SimVisionMS: Mixed Net Browser sort symbol is reversed
AVSREQ-131969 DMS_LICENSE license problem when using process-based save-and-restart
AVSREQ-165498 LP_1801 isolation location parent not honoured but self (terminalB context)
AVSREQ-155166 LP_1801 lps_cov is broken
AVSREQ-165036 SPECTRE_AMSD AMS: bus issue with sst2
AVSREQ-163297 SIMVISION_SCHEMATIC simvision schematic tracer "Center and Zoom after adding objects" option not working
AVSREQ-160874 DCP amsspice ERROR (SFE-868) because the file was not captured
AVSREQ-163541 DEBUG_DESIGN_DATABASE Indago stuck for 5 min when expanding the hierarchy tree
AVSREQ-152843 DMS_ELAB DMS IE Operation Fails with cds_rnm_packge::* types
AVSREQ-160857 LP_1801 xmelab: *SE,LPOVLG: [LPS] Advanced Low Power Verification is currently supported for VHDL and Verilog designs only.
AVSREQ-164133 DMS_LP_AMS Elab crash with xmelab: *E,CUVIMG (./rundir/INCA_libs/AMSD/cds_amslps_simulation.vp): Implicit name not allowed in hierarchical name.
AVSREQ-162090 SV_CODEGEN Xcelium21.03.011 and 21.09.004 crash during xmvlog.
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-154625 GLS_TIMING xmsim internal error when selecting DUT in Design Browser
AVSREQ-161421 LP_1801 MESSAGE: vst_name() - invalid class, class 688
AVSREQ-164049 LP_1801 Tool crash during elaboration after adding -lps_power_tchecks
AVSREQ-155766 LP_1801 LPVASRT error is seen during elaboration while dumping the coverage with lps_cov option
AVSREQ-159919 DEBUG_DESIGN_DATABASE Driver Tracing - VHDL signal tracing not working
AVSREQ-161226 ELAB_SV simulation internal error with Xcelium 21.09.003
AVSREQ-152873 GLS_TIMING Xcelium Simulation crash: Anonymous continuous assignment
AVSREQ-163710 LP_1801 xmsim: *E,LPSNORL when -lps_cov is used
AVSREQ-160428 DCP Rename .xmdcp directory to .dcp
AVSREQ-163616 DMS_ELAB xmelab *F INTERNAL EXCEPTION sss_hname - can't find AOI index (looks like AVSREQ-154490)
AVSREQ-164612 SIM_TCL The environment variable $TCLLIBPATH overridden by Xcelium
AVSREQ-150392 LP_1801 Using -lps_cov is resulting in LPOVLG Error
AVSREQ-155534 DMS_LP_AMS Crash during elaboration in SPICE+UPF sim with message: p_pot = NULL [NULL decl POT] - pwr_break_expr_vlog_etc
AVSREQ-163009 ELAB_SV xmsim: *E,RNDERR Randomization has encountered a bug: Internal error.
AVSREQ-157384 IP_PROTECT_GENERAL Xmvlog compile error for encrypted file
JIRA ID COMPONENT SUMMARY
AVSREQ-164447 SIMVISION_MS SimVisionMS: Mixed Net Browser sort symbol is reversed
AVSREQ-131969 DMS_LICENSE license problem when using process-based save-and-restart
AVSREQ-165498 LP_1801 isolation location parent not honoured but self (terminalB context)
AVSREQ-155166 LP_1801 lps_cov is broken
AVSREQ-165036 SPECTRE_AMSD AMS: bus issue with sst2
AVSREQ-163297 SIMVISION_SCHEMATIC simvision schematic tracer "Center and Zoom after adding objects" option not working
AVSREQ-160874 DCP amsspice ERROR (SFE-868) because the file was not captured
AVSREQ-163541 DEBUG_DESIGN_DATABASE Indago stuck for 5 min when expanding the hierarchy tree
AVSREQ-152843 DMS_ELAB DMS IE Operation Fails with cds_rnm_packge::* types
AVSREQ-160857 LP_1801 xmelab: *SE,LPOVLG: [LPS] Advanced Low Power Verification is currently supported for VHDL and Verilog designs only.
AVSREQ-164133 DMS_LP_AMS Elab crash with xmelab: *E,CUVIMG (./rundir/INCA_libs/AMSD/cds_amslps_simulation.vp): Implicit name not allowed in hierarchical name.
AVSREQ-162090 SV_CODEGEN Xcelium21.03.011 and 21.09.004 crash during xmvlog.
=========================================
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-164753 DMS_ELAB xmelab INTERR in reduced testcase for AVSREQ-163823
AVSREQ-149738 IP_PROTECT_GENERAL How to encrypt RTL code with module and its ports viewed in the encrypted code
AVSREQ-163652 GLS_SDF SDF Annotation is breaking IO realnet connections
AVSREQ-167089 SIMVISION_INFRA [XCELIUM][RHEL8.2]"simvision waves.shm -snapshot tb_mic NG" and " simvision FSM Window NG"
AVSREQ-166966 XPROPAGATION_GENERAL *W,XPNODC Warning is seen during simulation in spite of giving -ENABLE_XP_DEBUG_CODE in Primary elab in MSIE flow
AVSREQ-164720 ELAB_SV_VHDL Xcelium 21.09 SV macro elaboration fails but passes in version 21.03
AVSREQ-148618 SIMVISION_MS Analog results are not found in SimVision
AVSREQ-157261 SIM_PERFORMANCE Simulation results are different when using -enable_ff_split and -enable_async_ff_opt
AVSREQ-160428 DCP Rename .xmdcp directory to .dcp
AVSREQ-146768 SIMVISION_MS Design Browser: Need Show/Hide button in Design Browser Sidebar
AVSREQ-164336 SIM_PERFORMANCE Test failing with "-newperf" option
JIRA ID COMPONENT SUMMARY
AVSREQ-162752 SIMVISION_MS .svmspart.info generated even if ams_edb disabled
AVSREQ-168175 SIM_FORCE_RELEASE xmsim crashing with sslu_update_existing_hash/sslu_codprb_force backtrace
AVSREQ-115502 IP_PROTECT_GENERAL Ports are not visible when -autoprotect and -ip1735 are used combinedly
AVSREQ-162883 IP_PROTECT_GENERAL One encryption option that encrypt RTL file except IO ports and parameters
AVSREQ-163823 DMS_ELAB xmelab INTERR w/ Spice model
AVSREQ-167766 XPROPAGATION_GENERAL Different Xprop behavior W/WO protected RTL
AVSREQ-161421 LP_1801 MESSAGE: vst_name() - invalid class, class 688
AVSREQ-159201 IP_PROTECT_GENERAL Need support for -simulation portview/debugall with -ip1735 in xmprotect
AVSREQ-163094 SIM_PERFORMANCE Reset in always-statement is not evaluated correctly after power-up
AVSREQ-167507 HAL crashes on specific RTL; incorrectly indicates non-synthesizable constructions
AVSREQ-167569 LP_1801 strange warnings W,RECPROC in VHDL context
AVSREQ-164194 LP_1801 Isolation rule optimised away without an error *NOISELE
AVSREQ-163377 LP_VHDL UPF terminal boundary setting leads to glitches in the simulation (VHDL)
AVSREQ-162005 LP_1801 What are possible reasons when "set_isolation -source" filters ports that are driven by the given source?
AVSREQ-164967 LP_INFO_MODEL_AND_QUERY xmsim crash by using information model task upf_create_object_mirror
AVSREQ-167863 DMS_ELAB Xmelab crash with 21.09-s007
AVSREQ-163701 DMS_ELAB xmelab internal error during discipline resolution in digIs_merge_islands ()
AVSREQ-154415 DMS_SVAMS question about UDN connect module
AVSREQ-166922 DMS_LP_AMS xmelab crash : sv_seghandler - trapno -1 addr((nil))
AVSREQ-164606 GLS_SDF interconnect and ams fix
AVSREQ-164333 SIM_PERFORMANCE sim crash: csi-xmsim - CSI: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-165792 LP_1801 Isolation is being incorrectly inserted in power model / terminal boundary with -is_hard_macro
AVSREQ-163541 DEBUG_DESIGN_DATABASE Indago stuck for 5 min when expanding the hierarchy tree
AVSREQ-166244 DMS_ELAB testcase passes with 21.07 but crashes with 21.09
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-164753 DMS_ELAB xmelab INTERR in reduced testcase for AVSREQ-163823
AVSREQ-149738 IP_PROTECT_GENERAL How to encrypt RTL code with module and its ports viewed in the encrypted code
AVSREQ-163652 GLS_SDF SDF Annotation is breaking IO realnet connections
AVSREQ-167089 SIMVISION_INFRA [XCELIUM][RHEL8.2]"simvision waves.shm -snapshot tb_mic NG" and " simvision FSM Window NG"
AVSREQ-166966 XPROPAGATION_GENERAL *W,XPNODC Warning is seen during simulation in spite of giving -ENABLE_XP_DEBUG_CODE in Primary elab in MSIE flow
AVSREQ-164720 ELAB_SV_VHDL Xcelium 21.09 SV macro elaboration fails but passes in version 21.03
AVSREQ-148618 SIMVISION_MS Analog results are not found in SimVision
AVSREQ-157261 SIM_PERFORMANCE Simulation results are different when using -enable_ff_split and -enable_async_ff_opt
AVSREQ-160428 DCP Rename .xmdcp directory to .dcp
AVSREQ-146768 SIMVISION_MS Design Browser: Need Show/Hide button in Design Browser Sidebar
AVSREQ-164336 SIM_PERFORMANCE Test failing with "-newperf" option
JIRA ID COMPONENT SUMMARY
AVSREQ-162752 SIMVISION_MS .svmspart.info generated even if ams_edb disabled
AVSREQ-168175 SIM_FORCE_RELEASE xmsim crashing with sslu_update_existing_hash/sslu_codprb_force backtrace
AVSREQ-115502 IP_PROTECT_GENERAL Ports are not visible when -autoprotect and -ip1735 are used combinedly
AVSREQ-162883 IP_PROTECT_GENERAL One encryption option that encrypt RTL file except IO ports and parameters
AVSREQ-163823 DMS_ELAB xmelab INTERR w/ Spice model
AVSREQ-167766 XPROPAGATION_GENERAL Different Xprop behavior W/WO protected RTL
AVSREQ-161421 LP_1801 MESSAGE: vst_name() - invalid class, class 688
AVSREQ-159201 IP_PROTECT_GENERAL Need support for -simulation portview/debugall with -ip1735 in xmprotect
AVSREQ-163094 SIM_PERFORMANCE Reset in always-statement is not evaluated correctly after power-up
AVSREQ-167507 HAL crashes on specific RTL; incorrectly indicates non-synthesizable constructions
AVSREQ-167569 LP_1801 strange warnings W,RECPROC in VHDL context
AVSREQ-164194 LP_1801 Isolation rule optimised away without an error *NOISELE
AVSREQ-163377 LP_VHDL UPF terminal boundary setting leads to glitches in the simulation (VHDL)
AVSREQ-162005 LP_1801 What are possible reasons when "set_isolation -source" filters ports that are driven by the given source?
AVSREQ-164967 LP_INFO_MODEL_AND_QUERY xmsim crash by using information model task upf_create_object_mirror
AVSREQ-167863 DMS_ELAB Xmelab crash with 21.09-s007
AVSREQ-163701 DMS_ELAB xmelab internal error during discipline resolution in digIs_merge_islands ()
AVSREQ-154415 DMS_SVAMS question about UDN connect module
AVSREQ-166922 DMS_LP_AMS xmelab crash : sv_seghandler - trapno -1 addr((nil))
AVSREQ-164606 GLS_SDF interconnect and ams fix
AVSREQ-164333 SIM_PERFORMANCE sim crash: csi-xmsim - CSI: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-165792 LP_1801 Isolation is being incorrectly inserted in power model / terminal boundary with -is_hard_macro
AVSREQ-163541 DEBUG_DESIGN_DATABASE Indago stuck for 5 min when expanding the hierarchy tree
AVSREQ-166244 DMS_ELAB testcase passes with 21.07 but crashes with 21.09
====================================
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-152519 DMS_ELAB Using $temperature inside VAMS file in digital simulation causes crash
AVSREQ-171268 COVERAGE_FSM set_fsm_arc_scoring causing Xcelium to crash
AVSREQ-169211 GLS_SDF INTERNAL EXCEPTION in Xcelium 21.09 complains about parameterized bus statement
AVSREQ-169320 LP_ISOLATION Xcelium isolation insertion w/ -applies_to_boundary
AVSREQ-170587 COVERAGE_COVERGROUP INTERNAL EXCEPTION with coverage enabled
AVSREQ-164064 LP_1801 Weird b2b isolations w/ one on input of PA
AVSREQ-167452 XPROPAGATION_GENERAL signal does not wake up (x-> 0) even during the power on stage
AVSREQ-170874 LP_ISOLATION "set_repeater" on floating ports are not reported in lps_logfile
AVSREQ-159432 COVERAGE_CODE Need help explaining expression coverage results
AVSREQ-170115 SIMVISION_LOW_POWER Power switch missing in PSN when using for loop
AVSREQ-163280 DCP is not packing all needed files
AVSREQ-172147 SPECMAN_INTEF An umbrella option "-debug_opts indago_pp" makes a crash at xmsim
AVSREQ-172229 DMS_ELAB Spectre error with non-zero-based bus in AMS simulation
AVSREQ-163583 LP_1801 *E,SYNERRO error during xmlib2cdb of version
JIRA ID COMPONENT SUMMARY
AVSREQ-139355 COVERAGE_CODE Expression code coverage unexpected hole
AVSREQ-163703 LP_1801 NOISELE for one of the 3 scopes.
AVSREQ-170984 COVERAGE_FSM xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-170810 SIMVISION_MS Transient simulation hangs with Simvision MS
AVSREQ-164448 DEBUG_DESIGN_DATABASE Driver tracing is missing forces on a wire
AVSREQ-165751 SIM_SV Xcelium tool crash with Internal Exception error (when checking the BUS parameters)
AVSREQ-171615 LP_1801 Output terminal of IO cell on the Top hierarchy is an undefined value even if power is turned on.
AVSREQ-160774 COVERAGE_CODE unexplained expression coverage holes
AVSREQ-172099 DMS_AMSD xmvlog_cg crash with message gq_daca_metrics - vsp switch
AVSREQ-172317 DMS_ELAB connect modules lead to Cadence internal error during xmelab -> use -svams_2019 option to resolve -> -xmerror DPSVAP is not working, address it
AVSREQ-172122 SPECMAN_INTEF Backporting -debug_opts option for Xcelium 21.09 and Xcelium 22.03
AVSREQ-159112 LP_1801 Lot of signals dropped isolation, where CLP places. Need to fix all those
AVSREQ-170640 DOCUMENTATION sndefine
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-152519 DMS_ELAB Using $temperature inside VAMS file in digital simulation causes crash
AVSREQ-171268 COVERAGE_FSM set_fsm_arc_scoring causing Xcelium to crash
AVSREQ-169211 GLS_SDF INTERNAL EXCEPTION in Xcelium 21.09 complains about parameterized bus statement
AVSREQ-169320 LP_ISOLATION Xcelium isolation insertion w/ -applies_to_boundary
AVSREQ-170587 COVERAGE_COVERGROUP INTERNAL EXCEPTION with coverage enabled
AVSREQ-164064 LP_1801 Weird b2b isolations w/ one on input of PA
AVSREQ-167452 XPROPAGATION_GENERAL signal does not wake up (x-> 0) even during the power on stage
AVSREQ-170874 LP_ISOLATION "set_repeater" on floating ports are not reported in lps_logfile
AVSREQ-159432 COVERAGE_CODE Need help explaining expression coverage results
AVSREQ-170115 SIMVISION_LOW_POWER Power switch missing in PSN when using for loop
AVSREQ-163280 DCP is not packing all needed files
AVSREQ-172147 SPECMAN_INTEF An umbrella option "-debug_opts indago_pp" makes a crash at xmsim
AVSREQ-172229 DMS_ELAB Spectre error with non-zero-based bus in AMS simulation
AVSREQ-163583 LP_1801 *E,SYNERRO error during xmlib2cdb of version
JIRA ID COMPONENT SUMMARY
AVSREQ-139355 COVERAGE_CODE Expression code coverage unexpected hole
AVSREQ-163703 LP_1801 NOISELE for one of the 3 scopes.
AVSREQ-170984 COVERAGE_FSM xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-170810 SIMVISION_MS Transient simulation hangs with Simvision MS
AVSREQ-164448 DEBUG_DESIGN_DATABASE Driver tracing is missing forces on a wire
AVSREQ-165751 SIM_SV Xcelium tool crash with Internal Exception error (when checking the BUS parameters)
AVSREQ-171615 LP_1801 Output terminal of IO cell on the Top hierarchy is an undefined value even if power is turned on.
AVSREQ-160774 COVERAGE_CODE unexplained expression coverage holes
AVSREQ-172099 DMS_AMSD xmvlog_cg crash with message gq_daca_metrics - vsp switch
AVSREQ-172317 DMS_ELAB connect modules lead to Cadence internal error during xmelab -> use -svams_2019 option to resolve -> -xmerror DPSVAP is not working, address it
AVSREQ-172122 SPECMAN_INTEF Backporting -debug_opts option for Xcelium 21.09 and Xcelium 22.03
AVSREQ-159112 LP_1801 Lot of signals dropped isolation, where CLP places. Need to fix all those
AVSREQ-170640 DOCUMENTATION sndefine
=====================================
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-160820 IP_PROTECT_GENERAL xmprotect: Issues Memory Not Available
JIRA ID COMPONENT SUMMARY
AVSREQ-161604 IP_PROTECT_GENERAL Compile error in xmprotect file
AVSREQ-165791 VPI_GENERAL SimVision Design Browser crash upon expanding hierarchy
AVSREQ-174263 DMS_ELAB Improve CMINHR and CUVHNF messages with instances location
CCRID Product Title
–––––––- –––––––––––– –––––––––––––––––––––––––––
AVSREQ-160820 IP_PROTECT_GENERAL xmprotect: Issues Memory Not Available
JIRA ID COMPONENT SUMMARY
AVSREQ-161604 IP_PROTECT_GENERAL Compile error in xmprotect file
AVSREQ-165791 VPI_GENERAL SimVision Design Browser crash upon expanding hierarchy
AVSREQ-174263 DMS_ELAB Improve CMINHR and CUVHNF messages with instances location
Cadence's Xcelium Logic Simulation provides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments. Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium learns iteratively over an entire simulation regression. It analyzes patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles. Xcelium is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.
Accelerating DFT Simulations with Xcelium Multi-Core
Are long DFT simulations posing a big challenge to meet your tight project schedules? We have a solution to accelerate the long running DFT tests. Watch this video to know how easy it is to set-up Xcelium Multi-Core to get up to 5X acceleration for a variety of DFT use cases ranging from serial and parallel ATPG to MBIST and LBIST
Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.
Owner: Cadence
Product Name: XCELIUM
Version: 21.09.013 (XCELIUMMAIN) *
Supported Architectures: x86_64
Website Home Page : www.cadence.com
Languages Supported: english
System Requirements: Linux *
Size: 51.9 Gb
Base_XCELIUMMAIN21.09.001_lnx86
Hotfix_XCELIUMMAIN21.09.002_lnx86
Hotfix_XCELIUMMAIN21.09.003_lnx86
Hotfix_XCELIUMMAIN21.09.004_lnx86
Hotfix_XCELIUMMAIN21.09.005_lnx86
Hotfix_XCELIUMMAIN21.09.007_lnx86
Hotfix_XCELIUMMAIN21.09.008_lnx86
Hotfix_XCELIUMMAIN21.09.010_lnx86
Hotfix_XCELIUMMAIN21.09.013_lnx86
XCELIUM is simply a newer generation of the digital functional verification tools. Older versions were called INCISIVE. The last INCISIVE version was the 15.20 release, and there have been several XCELIUM releases since then. If using INCISIVE, you'd need to use "ncvhdl" instead of "xmvhdl".
Hotfix_XCELIUMMAIN21.09.002_lnx86
Hotfix_XCELIUMMAIN21.09.003_lnx86
Hotfix_XCELIUMMAIN21.09.004_lnx86
Hotfix_XCELIUMMAIN21.09.005_lnx86
Hotfix_XCELIUMMAIN21.09.007_lnx86
Hotfix_XCELIUMMAIN21.09.008_lnx86
Hotfix_XCELIUMMAIN21.09.010_lnx86
Hotfix_XCELIUMMAIN21.09.013_lnx86
XCELIUM is simply a newer generation of the digital functional verification tools. Older versions were called INCISIVE. The last INCISIVE version was the 15.20 release, and there have been several XCELIUM releases since then. If using INCISIVE, you'd need to use "ncvhdl" instead of "xmvhdl".
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Added by 3% of the overall size of the archive of information for the restoration
No mirrors please
Added by 3% of the overall size of the archive of information for the restoration
No mirrors please