Cadence Allegro and OrCAD 17.20.015 Update
Cadence Allegro and OrCAD 17.20.015 Update | 1.3 Gb
Cadence Design Systems, Inc. has released hotfix for OrCAD Capture, PSpice Designer and PCB Designer 17.2-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
Cadence OrCAD, Allegro, and Sigrity technologies and solutions provide unique, cost-effective, and scalable capabilities for designing some of the electronics industry's market-leading products.
With industry-proven OrCAD solutions, you get affordable yet sophisticated PCB technology, right from your desktop. Allegro PCB design solutions enable a constraint-driven design flow, from concept to manufacturing. Unique Sigrity technology provides the only proven path for system-level, power-aware signal integrity (SI)/simultaneous switching noise (SSN) compliance.
DATE: 03-16-2017 HOTFIX VERSION: 015
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CCRID Product ProductLevel2 Title
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1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol
1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout
1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
=================================================================
CCRID Product ProductLevel2 Title
=================================================================
1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol
1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout
1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence Allegro and OrCAD (Including EDM)
Version: 17.20.015 Update
Supported Architectures: 64bit
Website Home Page : www.cadence.com
Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even / 8 / 10 / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.001-2016 and above
Size: 1.3 Gb
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Added by 3% of the overall size of the archive of information for the restoration
No mirrors please
Cadence Allegro and OrCAD 17.20.015 Update
