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    Cadence OrCAD X Design Platform 2024.1 HF005 (24.10.005)

    Posted By: scutter
    Cadence OrCAD X Design Platform 2024.1 HF005 (24.10.005)

    Cadence OrCAD X Design Platform 2024.1 HF005 (24.10.005) | 5.6 Gb

    Cadence Design Systems, Inc. has released Cadence OrCAD X Design Platform 2024.1 HF005 (24.10.005) . This release includes fixes to various user-reported issues from the previous release, providing an overall more stable experience.

    3117744 ALLEGROX ASR_ROUTER ASR leaves DRCs, line to line, line to via, and T allowed at pins vias only
    3131237 ALLEGROX ASR_ROUTER Allegro Substrate Router does not obey the via at smd fit rule
    3131794 ALLEGROX ASR_ROUTER Allegro Substrate Router quits unexpectedly on stage 2 of routing
    3137885 ALLEGROX ASR_ROUTER Add ASR build information to asr.log file
    2507168 ALLEGROX DRC_CONSTR Enhancement to update 'Min neck width' to 'Min line/neck width and max neck length' in Analysis Modes
    2958761 ALLEGROX DRC_CONSTR PCB Editor quits unexpectedly when un-waiving minimum propagation delay DRC using DRC browser
    3022145 ALLEGROX DRC_CONSTR PCB Editor fails with import netlist; netrev.lst only reports '#1 Run stopped because errors were detected'
    3103144 ALLEGROX DRC_CONSTR Enhance spacing constraints to allow user to specify a tolerance or allowed length for line to route keepin overlap
    3126084 ALLEGROX DRC_CONSTR Microvia to microvia slot DRCs are not being suppressed/flagged as expected in certain cases
    3133318 ALLEGROX DRC_CONSTR Allegro X Waived DRC's do not remove DRC Lines.
    3126537 ALLEGROX DXF Drill information missing in DXF export
    3115289 ALLEGROX EDIT_ETCH The delay tune matching is not reflected in Constraint Manager
    3150070 ALLEGROX EDIT_ETCH CuMax not generating all tabs
    3002628 ALLEGROX GRAPHICS Drill Labels for Slotted Padstacks should repeat along slot length so it is seen when padstack origin is not in view
    3122381 ALLEGROX GRAPHICS Update PGU plugin to check that NV_PLUGIN_PATH environment variable matches the layout editor version being launched
    2829515 ALLEGROX IN_DESIGN_ANA Aurora-DCIR-Drop-Flow Result Table, Auto Filter the Power Path for Selected Failed Sink
    2857505 ALLEGROX IPC IPC-2581 export should take artwork pad suppression into account and override cross section setting
    3135565 ALLEGROX MARKUP Enhancement to disable Cadence login window in Presto
    3143804 ALLEGROX MARKUP Request for an Option to disable Cadence login window to connect to cloud at program launch in OrCAD X Presto.
    2912684 ALLEGROX MCAD_COLLAB Importing IDX file either takes a very long time or causes PCB Editor to quit unexpectedly
    3069485 ALLEGROX MCAD_COLLAB Through-hole length discrepancy between board thickness and IDX data exported from PCB Editor
    3078648 ALLEGROX MCAD_COLLAB IDX import causing the layout editor to quit unexpectedly
    3111511 ALLEGROX OTHER "Design workflow schema not found, provide valid schema file" error after installing release 24.1 hotfix 002
    3058111 ALLEGROX SHAPE "Void must be within the shape" error when importing IDX that contains shapes with different Z axis heights
    3101697 ALLEGROX SKILL axlCanvasPrintToPDF multipage PDF
    3121673 ALLEGROX SKILL Layout editor quits unexpectedly when running 'exit axlTrigger that contains axkShell("done") in it.
    3125209 APD ASR_ROUTER ASR to use dangling clines as starting points to complete partially routed nets
    3115384 APD DEGASSING Allow users to adjust global dynamic shape parameters GUI
    3115414 APD DEGASSING Exclude dielectric layers from layer-pattern assignment
    3116169 APD DEGASSING Highlight row of selected pattern in layer based degas/metal fill table
    3145505 APD DRC_CONSTRAIN External microvias with core microvias causing false DRCs
    3088703 APD DXF_IF Drill legend export DXF issue
    3117606 APD OTHER Display > Min Airgap does not correctly report the minimum air gap.
    3091180 APD REPORTS Metal Usage Report not reverting unit from design units.
    3128032 APD SHAPE Shape to cline segment voiding oversize issue
    3124986 APD STREAM_IF stream out failed through the Selected Area / Visible Window
    3125993 APD STREAM_IF Bug - Import Stream file
    3117288 APD VIA_STRUCTURE Replacing via in design takes over 16 hours making the flow unusable for users
    3118932 APD WLP Metal fill is applied on cline instead of gap between shape & cline
    3129289 APD WLP Package Integrity Check: False alarm DRC for stacking items with cline
    3127358 CAPTURE CORRUPT_DESIG Capture quits unexpectedly during cache cleanup and replace operations in the attached design
    3122101 CAPTURE PARTAUTHORING Components added from "add to library" command do not show footprint when RMB show footprint is done on placed instance
    3125044 CAPTURE WORKSPACECONF Component database stuck in download state when accessing my Workspace in Component Explorer
    3134338 CLOUD_INFRA STARTPAGE Certificate error upon launching a layout editor
    3148460 CLOUD_INFRA SYMPHONY It appears that OrCAD X Presto 24.1 hotfix 3 is infected with malware
    3151756 CLOUD_INFRA SYMPHONY Launching Symphony Connect in OrCAD X Presto generates a WITH-LOVE-FROM-AMERICA.txt file
    3146314 CONSTRAINT_MGR TOPOLOGY System Capture quits unexpectedly when saving design after updating constraints from Topology Explorer
    3127481 CONSTRAINT_MGR UI_FORMS Create new Analysis Mode option under Design > Spacing Option for axlSetThievingSpacing/axlGetThievingSpacing
    3136322 LIVEDOC EXPORT Font style in title block is not correctly passed to PDF export; bold is exported as underline
    2989827 PSPICE SIMULATOR ORPSIM-15142: Node is floating error in Infineon model
    3024189 PSPICE SIMULATOR Delayed Simulation start: Stops responding at Reading and Checking Circuit
    3132948 PSPICE SIMULATOR Checkpoint Restart: Simulation will not restart from stateX because the topology of the circuit has been changed
    3141077 PULSE R2PLM-3DX Unable to map Teamcenter attributes to PFM in release 24.1
    3056793 PULSE R2PLM-TC PFM Summary report does not indicate items that were skipped and the reason they were skipped during publish.
    2932144 PULSE R2PLM-WC PFM-1073 and PFM-122 error during Publish For Manufacturing.
    2956030 PULSE R2PLM-WC ERROR PFM-1036: Cannot publish to PTC Windchill
    3096108 PULSE R2PLM-WC Skip ITEM NUMBER validation on Document objects with no attachment to be published
    3117088 PULSE R2PLM-WC PFM Mandatory utilities are not honored correctly
    3116240 PULSE UNIFIED_SEARC Feature request to expose api to control what the "Details Panel" in system capture displays
    3163247 PULSE_SERVER APP_SRM ExportModels is giving error while loading shared libraries: libnode.so.83
    2768299 SYSTEM_CAPTURE ALIGN_DISTRIB NetName justification changes during PDF plotting
    3118551 SYSTEM_CAPTURE ARCHIVER Trying to archive the design makes no difference and System Capture stops responding
    3132501 SYSTEM_CAPTURE CAPTURE_SUPPO Setting up TitleBlock in OrCAD X Capture-based System Capture schematic using site.cpm by default is not working
    3144373 SYSTEM_CAPTURE CAPTURE_SUPPO Capture-based custom library should be read from site.cpm in the standalone System Capture environment
    3159814 SYSTEM_CAPTURE CRASHLOGGER System Capture quits unexpectedly after Part Manager update
    3161252 SYSTEM_CAPTURE CRASHLOGGER The application quit unexpectedly after selecting OK to update Part Manager
    3156105 SYSTEM_CAPTURE DARK_THEME Schematic Sheet background in NSE comes white and so part objects are not visible in SPB 23.1 ISR 9 and 10
    3156544 SYSTEM_CAPTURE DARK_THEME Symbol view in synbol editor is not visible becuase of high contrast even in black theme.
    3161031 SYSTEM_CAPTURE DARK_THEME NSE background is white and so part is not visible
    3133653 SYSTEM_CAPTURE IMPORT_DEHDL_ Cannot import unnamed nets that have a comma in the symbol name
    3133574 SYSTEM_CAPTURE PACKAGER cpb::queryPartPropsFromSpath returns empty value for all variants when variant symbol is the manual sync state
    3133581 SYSTEM_CAPTURE PACKAGER Add lib/cell info from the Physical View API
    3154354 SYSTEM_CAPTURE PACKAGER A few components inside the block have no suffix.
    3104327 SYSTEM_CAPTURE PAGE_BORDER move blocks outside the page border to another place will make the refdes change which will impact existing PCB layout
    2954627 SYSTEM_CAPTURE PART_MANAGER Part Manager update fails to recover corrupted schematic database components
    3066368 SYSTEM_CAPTURE PART_MANAGER Properties highlighted in orange in Attributes panel
    3128144 SYSTEM_CAPTURE PART_MANAGER Enhancements needed for pacman command
    3127355 SYSTEM_CAPTURE PROPERTY_EDIT Signal not getting changed from power to normal
    3125040 SYSTEM_CAPTURE REPORTS Creating reports, such as a BOM, from dsreportgen, displays an error about incorrect worklib path
    3126913 SYSTEM_CAPTURE SCRIPTING tcl running in graph vs nograph produces different results.
    3114663 SYSTEM_CAPTURE SHORTCUTS No shortcut for Ascend
    3144857 SYSTEM_CAPTURE TOPXP Topology Explorer print dialog box needs improvement
    3091752 SYSTEM_CAPTURE UI Table text colors are not rendered correctly in System Capture dark mode.
    3021180 SYSTEM_CAPTURE VARIANT_MANAG System Capture - DNP text instead of crossmark 
    3043094 SYSTEM_CAPTURE VARIANT_MANAG Place property variant DNI instead of cross (X) on component in variant view.
    3115446 SYSTEM_CAPTURE VARIANT_MANAG Variant functions appeared in design after upgrading from 22.1 to 23.1 release.
    3128136 SYSTEM_CAPTURE VARIANT_MANAG System Capture Variant View in schematic canvas is not displaying all pin numbers
    3134163 SYSTEM_CAPTURE VARIANT_MANAG Need to be able to specify user-specific variant property name and value, and DNI value for System Capture
    3143130 SYSTEM_CAPTURE VARIANT_MANAG Including a DNI/DNF text information near the part when editing in the variant view
    2972857 SYSTEM_CAPTURE WIRING 4-way connections are shorted
    3125955 SYSTEM_CAPTURE WIRING System Capture wire section auto-name enhancement
    3128734 SYSTEM_CAPTURE WIRING System Capture unintended short and 4way connection
    3125824 SYS_RELIABILITY STRESS_ANALYS Ignoring 'CXX' because it is part of 'subcircuitX', which had a simulation failure.
    3115948 TOPXP GUI Symbols, such as SnP block, do not appear on the screen
    3150942 TOPXP SYSTEMSI Simulation on the attached SSI design results in grayed out folders and no plot
    3145497 TOPXP TOPOLOGY_EXPL Issue with port name changes during broadband SPICE extraction in Topology Workbench 24.1 hotfix 003
    3146263 TOPXP TOPOLOGY_EXPL GND net issue in Topology Explorer

    OrCAD X and Allegro X are the latest upgrades from the respective Cadence circuit design software.
    OrCAD X is the latest release of the OrCAD design platform, intended to provide designers with a best-in-class and comprehensive PCB design and layout environment with the new OrCAD X Presto PCB Editor. The focus of OrCAD X is to streamline and simplify the usability and customization of tools to keep designers engaged with the board design. The new user interface makes it easy to accelerate printed circuit development .
    Allegro X offers additional functionality, but both are extremely capable of meeting the challenges of modern-day printed circuit DFM. Designers interested in OrCAD X or Allegro X are well served to see how easy and powerful circuit design can be. And just like their predecessors, OrCAD X and Allegro X have the support of Cadence’s PCB Design and Analysis Software for a seamless and thorough dsign process.

    OrCAD X


    Learn about the OrCAD X Platform and see how it's capabilities and easy to use interface help you design fast, correct and connected.
    Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For.

    Owner: Cadence
    Product Name: OrCAD X Design Platform (OrCAD X and Allegro X)
    Version: 2024.1 HF005 (24.10.005) with Documentation
    Supported Architectures: x64
    Website Home Page : www.cadence.com
    Languages Supported: english
    System Requirements: Windows *
    Software Prerequisites: pre-installed OrCAD X Design Platform 2024 (24.10.000) Base Release
    Size: 5.6 Gb

    Cadence OrCAD X Design Platform 2024.1 HF005 (24.10.005)

    Cadence OrCAD X Design Platform 2024 (24.10.000)

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    Cadence OrCAD X Design Platform 2024.1 HF005 (24.10.005)