Cadence OrCAD X Platform 2023 (23.10.001)
Cadence OrCAD X Platform 2023 (23.10.001) | 12.6 Gb
Cadence Design Systems, Inc. announced the new Cadence OrCAD X Platform, a cloud-enabled system design solution that offers transformative improvements in ease of use, performance, automation and collaboration. The new OrCAD X Platform streamlines the system design process and empowers designers through cloud scalability and AI-powered placement automation technology, enabling up to 5X reduction in design turnaround time.
With significantly higher productivity enabled by cloud-connected capabilities—including data management, collaborative layout design and a new easy-to-use layout environment optimized for small and medium businesses—this next-generation platform includes everything in the OrCAD platform and more. Supercharged with powerful layout productivity improvements based on the Cadence Allegro® X Platform, it provides complete backward data compatibility with OrCAD and Allegro technologies.
The new OrCAD X platform provides the following benefits:
- Cloud-enabled: Improves productivity with real-time access to data management via the Cadence OnCloud Platform. Data storage and management through a cloud login enables a hybrid work environment across the desktop and the cloud, reducing infrastructure costs for the user.
- Ease of use: Optimized for small and medium businesses, the OrCAD X platform offers a new, easy-to-learn and easy-to-use PCB layout canvas while retaining the power of industry-proven engines. New cloud-based licensing options are available as well as many user-experience enhancements from installation through design. The dynamic creation of manufacturing documentation provides a real-time view of fabrication details throughout the entire design process.
- Faster turnaround time: Significantly enriched electrical constraints, performance improvements and integration with the broader Cadence system design and analysis portfolio enable faster time to market.
- Collaboration: Cloud-hosted collaboration allows multiple designers to work concurrently on the same layout design.
The OrCAD X platform can access automated placement through the Allegro X AI system, which enables transformative placement time reduction from days to minutes. Users can achieve these placement time reductions while simultaneously addressing signal integrity, power integrity and thermal design effects during placement, routing of critical signals and the generation of power planes.
The AI-based OrCAD X platform supports Cadence’s Intelligent System Design strategy, which enables customers to accelerate system innovation.
Release-Level Changes
- Introduces the new OrCAD X platform and its new layout application, OrCAD X Presto. OrCAD X is a Cloud-enabled innovative platform that caters to individual designers and small to mid-size businesses. OrCAD X Presto, the new layout application within the platform, offers flexible design options, ranging from cloud-based connections to unconnected modes. OrCAD X Presto is fully compatible with existing layout applications, ensuring easy transition of layout designs.
- Branding changes have been made to OrCAD and Allegro programs and applications, re-branding them to OrCAD X and Allegro X.
- Product Start pages include links to the latest versions, making it easier to check for updates and then download to update to the latest versions. Help menus also include the Check For Updates.
- Added a new product documentation viewer, Cadence Doc Assistant. This cloud-based application not only displays the content installed but also seamlessly retrieves the latest content available on Cadence servers, depending on your connectivity and setup.
Allegro X PCB and Allegro X Advanced Package Designer
- New analysis modes and checks for zone adherence of symbol pins are added for Rigid-Flex designs. Support is added for nested zones that have different masking, plating, or stack-up requirements from the rest of the zone. Also added is the support for standard shape commands on zones. Fill-In Material in Cross-section Editor can now source the common materials file (.cmx).
- 3DX Canvas has packaging support for objects, such as wire bonds, ball, die bump, pillar geometries, die stacks, etch back, and so on. New 3D DRCs are added to Constraint Manager, namely, Wire to Wire, Wire to Finger, Wire to Shape, Wire to Cline, and Wire to Component.
- Fillets are dynamically updated while routing to meet silicon fillet rules; you can dynamically add tapered trace fillets when working with Allegro X Advanced Package Designer with the Silicon Layout option.
- In Padstack Editor, you can define counterbore or countersink from the primary or secondary side; it is no longer bound to the side the component is placed on. The Drill Legend and NC Drill features indicate if drilling is required from the secondary side, eliminating the need to inform the fabricator about secondary drilling requirements. You can now use oval and rectangular slots in microvia padstack.
- You can freeze dynamic shapes without changing them to static in situations where you must maintain design intent and protect critical circuitry drawn using shapes.
- The Design Review and Markup feature is added for reviewing designs through markups. You can even review the markup with canvas auto-centering and layer display.
- Various usability enhancements are available in the areas of 3D canvas, 3D model export, dimensioning environment, copying etch shapes to layers, converting lines or clines to shapes, netlist imports from external sources, new reports, and many others.
- New high-voltage constraints to verify creepage and clearance are available in Allegro X. The DRC system recognizes non-plated slots between two high-voltage objects and recalculates creepage around the slots. The Creepage/Clearance Vision option provides color-coded information to review the DRC errors.
- Managing library change impact on board designs is simplified with Symbol Revision Manager (SRM) integrated with Allegro X PCB Editor connected to Allegro X Pulse server.
Sigrity Aurora
- A new Sigrity XtractIM workflow offering quick package design parasitic analysis is added to Allegro X Advanced Package Designer. Two new analyses are also supported, Per Pin (Die-side Power) and Per Net (Signal).
- Power Inductance workflow and Topology Extraction workflow are now available in Allegro X PCB Editor and Sigrity Aurora in Allegro X Advanced Package Designer.
Allegro X Pulse
- Two-way synchronization support between Allegro EDM and PTC Windchill data is added.
- The web dashboard is enhanced. Project and Design views are added to display project containers and Pulse-managed designs, including schematics and layouts. New filters and controls are added for organizing columns. Project-specific URLs are available, making it easier to share and bookmark designs.
- The new project from template feature includes Pulse-managed layouts that are linked to a project through the Pulse netlist exchange flow. The required layouts can be carried over to a new project.
Allegro X System Capture
- Topology Workbench has replaced Signal Explorer for analyzing the signal integrity of high-speed nets at the schematic, floorplan, and layout stages. You can launch Topology Workbench directly for a single net or XNet or from Constraint Manager.
- A new capability is introduced to generate a thermal floorplan for a board associated with a schematic, using Celsius Thermal Solver.
- Two new analyses are included: MTBF analysis and Power Topology analysis. MTBF analysis predicts the performance and safety of electrical, mechanical, and electro-mechanical parts. Power Topology sets up a power distribution network on the schematic and estimates the DC power consumption by the PCB design components.
- Integrated library authoring continues to be scaled up. It now includes support for templates, categories, spreadsheet-based editing, custom shapes, and pin shapes. This release also includes enhanced validation checks.
- Designers in multi-user environments no longer need to be connected to the Pulse server all the time. They can work offline and connect back to the server and synchronize their design and library data.
- Managed layouts are now visible in the Project Explorer pane of System Capture, making it easier to stay updated with the changes in the layouts associated with schematics.
- To enable easier decision-making for team design updates, you can now compare design versions. You can also compare a design or individual blocks with the previous or latest committed versions.
- Unified Search can now scan libraries as well as design data. While querying design data, Unified Search reads metadata, such as Pulse attributes and custom variables, and design data, such as voltages, nets, components, NetGroups, and block attributes. The search results are displayed in a new Design tab. This deep search enables powerful IP exploration and identification of reuse opportunities.
Topology Workbench
- In Sigrity SystemSI technology, eye mask support is added to 3D eye density plots. Compliance Kits workflow supports USB 4 - Gen 4 Compliance Kit.
- CSV data from AMI models can now be imported into waveforms.
- In Sigrity SystemPI, technology support is added for new VRM models. Two operational amplifier (op amp) blocks have been added to model voltage regulator modules (VRM) more accurately. VRM blocks, such as Ideal Supply (VDC) VRM, RL VRM, RL//RL VRM, and Subckt VRM are also updated.
- A new floating toolbar has replaced the Add Block panel.
PSpice A/D
- Modeling Application supports digital devices and sources. You can model digital devices, such as gates, flip flops, latches, and sources, and place them on the schematic.
- PSpice simulator supports varying temperatures with time in a single transient run.
- Support for two components, IEXP_B and VEXP_B, is added for modeling exponential voltage or a current source.
- A new option, EXPR_DEBUG, is added for enhanced debugging of convergence errors. Using this helps you easily find the exact expression in the warning message that is causing an error.
OrCAD X Capture CIS
- A complete part authoring environment is available. You can create new categories and components from scratch or add components from content providers, including SnapEDA, SamacSys, and Ultra Librarian.
- Working with teams is simplified with a collaborative development environment where you can create shared workspaces and share library and design data. Using the Cloud workspace functionality, you can also create component libraries for teams.
- The Cloud-enabled workspace data is accessible from anywhere. The background data sync utility keeps the data in sync between the local disk and the Cloud.
- Support is added for Live BOM, a dynamic bill of materials (BOM), which is generated using supply chain data from SourceEngine.
- From OrCAD X Capture CIS, you can quickly and easily publish your design data to a 3D EXPERIENCE PLM server to provide up-to-date design information to various stakeholders.
- Introduces the new OrCAD X platform and its new layout application, OrCAD X Presto. OrCAD X is a Cloud-enabled innovative platform that caters to individual designers and small to mid-size businesses. OrCAD X Presto, the new layout application within the platform, offers flexible design options, ranging from cloud-based connections to unconnected modes. OrCAD X Presto is fully compatible with existing layout applications, ensuring easy transition of layout designs.
- Branding changes have been made to OrCAD and Allegro programs and applications, re-branding them to OrCAD X and Allegro X.
- Product Start pages include links to the latest versions, making it easier to check for updates and then download to update to the latest versions. Help menus also include the Check For Updates.
- Added a new product documentation viewer, Cadence Doc Assistant. This cloud-based application not only displays the content installed but also seamlessly retrieves the latest content available on Cadence servers, depending on your connectivity and setup.
Allegro X PCB and Allegro X Advanced Package Designer
- New analysis modes and checks for zone adherence of symbol pins are added for Rigid-Flex designs. Support is added for nested zones that have different masking, plating, or stack-up requirements from the rest of the zone. Also added is the support for standard shape commands on zones. Fill-In Material in Cross-section Editor can now source the common materials file (.cmx).
- 3DX Canvas has packaging support for objects, such as wire bonds, ball, die bump, pillar geometries, die stacks, etch back, and so on. New 3D DRCs are added to Constraint Manager, namely, Wire to Wire, Wire to Finger, Wire to Shape, Wire to Cline, and Wire to Component.
- Fillets are dynamically updated while routing to meet silicon fillet rules; you can dynamically add tapered trace fillets when working with Allegro X Advanced Package Designer with the Silicon Layout option.
- In Padstack Editor, you can define counterbore or countersink from the primary or secondary side; it is no longer bound to the side the component is placed on. The Drill Legend and NC Drill features indicate if drilling is required from the secondary side, eliminating the need to inform the fabricator about secondary drilling requirements. You can now use oval and rectangular slots in microvia padstack.
- You can freeze dynamic shapes without changing them to static in situations where you must maintain design intent and protect critical circuitry drawn using shapes.
- The Design Review and Markup feature is added for reviewing designs through markups. You can even review the markup with canvas auto-centering and layer display.
- Various usability enhancements are available in the areas of 3D canvas, 3D model export, dimensioning environment, copying etch shapes to layers, converting lines or clines to shapes, netlist imports from external sources, new reports, and many others.
- New high-voltage constraints to verify creepage and clearance are available in Allegro X. The DRC system recognizes non-plated slots between two high-voltage objects and recalculates creepage around the slots. The Creepage/Clearance Vision option provides color-coded information to review the DRC errors.
- Managing library change impact on board designs is simplified with Symbol Revision Manager (SRM) integrated with Allegro X PCB Editor connected to Allegro X Pulse server.
Sigrity Aurora
- A new Sigrity XtractIM workflow offering quick package design parasitic analysis is added to Allegro X Advanced Package Designer. Two new analyses are also supported, Per Pin (Die-side Power) and Per Net (Signal).
- Power Inductance workflow and Topology Extraction workflow are now available in Allegro X PCB Editor and Sigrity Aurora in Allegro X Advanced Package Designer.
Allegro X Pulse
- Two-way synchronization support between Allegro EDM and PTC Windchill data is added.
- The web dashboard is enhanced. Project and Design views are added to display project containers and Pulse-managed designs, including schematics and layouts. New filters and controls are added for organizing columns. Project-specific URLs are available, making it easier to share and bookmark designs.
- The new project from template feature includes Pulse-managed layouts that are linked to a project through the Pulse netlist exchange flow. The required layouts can be carried over to a new project.
Allegro X System Capture
- Topology Workbench has replaced Signal Explorer for analyzing the signal integrity of high-speed nets at the schematic, floorplan, and layout stages. You can launch Topology Workbench directly for a single net or XNet or from Constraint Manager.
- A new capability is introduced to generate a thermal floorplan for a board associated with a schematic, using Celsius Thermal Solver.
- Two new analyses are included: MTBF analysis and Power Topology analysis. MTBF analysis predicts the performance and safety of electrical, mechanical, and electro-mechanical parts. Power Topology sets up a power distribution network on the schematic and estimates the DC power consumption by the PCB design components.
- Integrated library authoring continues to be scaled up. It now includes support for templates, categories, spreadsheet-based editing, custom shapes, and pin shapes. This release also includes enhanced validation checks.
- Designers in multi-user environments no longer need to be connected to the Pulse server all the time. They can work offline and connect back to the server and synchronize their design and library data.
- Managed layouts are now visible in the Project Explorer pane of System Capture, making it easier to stay updated with the changes in the layouts associated with schematics.
- To enable easier decision-making for team design updates, you can now compare design versions. You can also compare a design or individual blocks with the previous or latest committed versions.
- Unified Search can now scan libraries as well as design data. While querying design data, Unified Search reads metadata, such as Pulse attributes and custom variables, and design data, such as voltages, nets, components, NetGroups, and block attributes. The search results are displayed in a new Design tab. This deep search enables powerful IP exploration and identification of reuse opportunities.
Topology Workbench
- In Sigrity SystemSI technology, eye mask support is added to 3D eye density plots. Compliance Kits workflow supports USB 4 - Gen 4 Compliance Kit.
- CSV data from AMI models can now be imported into waveforms.
- In Sigrity SystemPI, technology support is added for new VRM models. Two operational amplifier (op amp) blocks have been added to model voltage regulator modules (VRM) more accurately. VRM blocks, such as Ideal Supply (VDC) VRM, RL VRM, RL//RL VRM, and Subckt VRM are also updated.
- A new floating toolbar has replaced the Add Block panel.
PSpice A/D
- Modeling Application supports digital devices and sources. You can model digital devices, such as gates, flip flops, latches, and sources, and place them on the schematic.
- PSpice simulator supports varying temperatures with time in a single transient run.
- Support for two components, IEXP_B and VEXP_B, is added for modeling exponential voltage or a current source.
- A new option, EXPR_DEBUG, is added for enhanced debugging of convergence errors. Using this helps you easily find the exact expression in the warning message that is causing an error.
OrCAD X Capture CIS
- A complete part authoring environment is available. You can create new categories and components from scratch or add components from content providers, including SnapEDA, SamacSys, and Ultra Librarian.
- Working with teams is simplified with a collaborative development environment where you can create shared workspaces and share library and design data. Using the Cloud workspace functionality, you can also create component libraries for teams.
- The Cloud-enabled workspace data is accessible from anywhere. The background data sync utility keeps the data in sync between the local disk and the Cloud.
- Support is added for Live BOM, a dynamic bill of materials (BOM), which is generated using supply chain data from SourceEngine.
- From OrCAD X Capture CIS, you can quickly and easily publish your design data to a 3D EXPERIENCE PLM server to provide up-to-date design information to various stakeholders.
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CCRID Product ProductLevel2 Title
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2796563 ALLEGRO_EDITOR 3D_CANVAS 3D Rendering of layers appears incorrect.
2733652 ALLEGRO_EDITOR CROSS_SECTION In multi stackups mode All stackups tab is not showing all the stackups.
2796566 ALLEGRO_EDITOR CROSS_SECTION All Stackups tab does not show all stackups in the design.
2849582 ALLEGRO_EDITOR DATABASE Netlist import doesn't finish
2695403 ALLEGRO_EDITOR DFA DFA Placebound to Pastemask DRC
2773520 ALLEGRO_EDITOR DFA DFA Bubble not honoring multisided shape properly
2800298 ALLEGRO_EDITOR DFA DFA table is migrated to Constraint manager not showing DFA Bubble DRC during placement
2797313 ALLEGRO_EDITOR DFM Remove the legacy DFA table after migrating into the constraint manager DFA?
2856300 ALLEGRO_EDITOR DFM DFF Copper Spacing not picking up on via to shape of same net DRC
2848937 ALLEGRO_EDITOR EDIT_ETCH Cline bubble or hug around mechanical hole
2872449 ALLEGRO_EDITOR EDIT_ETCH Timing vision is bugged once "Enable Static Phase at Vias option" is enabled.
2593126 ALLEGRO_EDITOR GRAPHICS Shapes not highlighted when using "Reject" in GPU-mode (Linux).
2724555 ALLEGRO_EDITOR GRAPHICS SOV highlight displays odd behavior
2741223 ALLEGRO_EDITOR GRAPHICS Assign Color/Highlight Bundles in Allegro PCB Venture in 17.4 does not work with GPU enabled
2865769 ALLEGRO_EDITOR GRAPHICS Temp highlight behavior has no transparency
2872564 ALLEGRO_EDITOR GRAPHICS part of bundle flow not visible while in GPU mode
2867657 ALLEGRO_EDITOR IPC Enhancement to Output of drilled hole size and plating thickness to IPC-2581
2805884 ALLEGRO_EDITOR MCAD_COLLAB Shape subclass changing after importing IDF file
2853984 ALLEGRO_EDITOR MCAD_COLLAB IDX 4.0 import issue with Onshape tool
2880362 ALLEGRO_EDITOR MCAD_COLLAB IDF Import on Flex design with zone using Multi cross-section swaps symbols shapes incorrectly
2810059 ALLEGRO_EDITOR SHAPE Thermal ties not as expected
2838112 ALLEGRO_EDITOR UI_GENERAL Paste not working in telskill window
2863683 ALLEGRO_EDITOR UI_GENERAL axlUIMultipleChoice - giving wrong return value upon escape/cancel
2865778 ALLEGRO_EDITOR UI_GENERAL Include user env setting to auto clear search string in find by name textbox when enter is pressed
2866911 ALLEGRO_EDITOR UI_GENERAL “Paste” does not work in the SKILL (set telskill) window (SPB22.1 HF6)
2865644 ALLEGRO_EDITOR VIA_STRUCTURE Issue with eXML file generation for high-speed via structure in Allegro
2700354 APD ASSY_RULE_CHE Degassing void overlap issue
2713336 APD ASSY_RULE_CHE Slow performance with void-void spacing
2867235 APD ASSY_RULE_CHE Assembly rule checker is taking too long to run
2831000 APD DEGASSING Create a new SKILL API for the equivalant to erase Adv Degassing holes
2833487 APD DEGASSING APD tool is crashing when doing degassing>shape update
2867204 APD DEGASSING Advanced shape degassing is crashing APD+
2876179 APD INTERACTIVE Netin crashes on the attached design
2903349 APD IN_DESIGN_ANA About the display of System Configuration Editor
2872861 APD MULTI_USER Symphony rejection issues when deleting vias
2851011 APD STREAM_IF Suppress unconnected pads option and Stream Out
2867199 APD STREAM_IF Missing degassing holes on GDS file
2877139 APD STREAM_IF Pad Degassing not showing correctly in the stream out file
2854817 ASI_SI GUI Unable to set material properties for solderbump and ball in APD for XIM extraction
2790801 CONCEPT_HDL CORE When I try to mark a top level block instance as DNI in the variant schematic view. ConcptHDL crashes..
2831459 CONCEPT_HDL CORE space at the beginning of the sentence is deleted.
2848319 CONCEPT_HDL CORE Cadence HDL 22.1 ISR 005 - Crash
2850517 CONCEPT_HDL CORE Why is net PWR_CNT not in net group HV_GRP1 in the constraint manager. It has that net_group attribute on the net. It wa
2793171 CONCEPT_HDL OTHER Variant editor and marking components as variants and DNI causing DEHDL to crash
2844121 CONCEPT_HDL OTHER Process gets stuck with 22.1 while running tcl commands
2864910 CONSTRAINT_MGR SYSCAP NetClass shows stale members when using SKILL API to query members
2893851 PCB_LIBRARIAN LIBDB_CORE "BPC23_LIB" Pin length is not suitable from "Add pin" button
2858871 PCB_LIBRARIAN SYMBOL_EDITOR Support Allegro System Capture to OrCAD Capture translation for zero-length pin stubs.
2762447 PCB_LIBRARIAN SYMBOL_EDITOR Cant change documentation grid in NSE
2820516 PCB_LIBRARIAN SYMBOL_EDITOR Documentation grid is incorrect in NSE
2807043 PCB_LIBRARIAN SYM_CREATOR_C Executing expand vector pin is slow in new Symbol Editor
2807073 PCB_LIBRARIAN SYM_CREATOR_C The move command is slow for pin numbers in new Symbol Editor
2102930 PSPICE AA_MC PSpice AA Monte Carlo slow compared to standard MC
2195199 PSPICE AA_MC Advanced Analysis Monte Carlo performance is slow as compared to standard MC
2781887 PSPICE AA_MC Enhancement for speed improvement of PSpiceAA MC runs.
2841035 PSPICE AA_MC PSpice AA MC is significantly slower than PSpice MC
2841038 PSPICE AA_MC PSpice AA MC is significantly slower than PSpice MC
2893141 PSPICE ENVIRONMENT Unable to launch PSpice Basic version with license ALG200
1375245 PSPICE MODELEDITOR Improve error message while saving file if backup directory is read only
2179166 PSPICE NETLISTER PSpice Netlist Error but nothing in Session Log for attached testcase
1188042 PSPICE SIMULATOR INTERNAL ERROR – Overflow Convert
2191276 PSPICE SIMULATOR Inconsistent bias point results with Vpulse source.
2238626 PSPICE SIMULATOR Tolerance of BJT's param from model is not taken account in PSpice Advanced Analysis v17.4 Assign Tolerance
2243592 PSPICE SIMULATOR Long .param statement in .include file NOT included, with no warning or error.
2657100 PSPICE SIMULATOR PSpice Monte Carlo error "Illegal parameter value in input file"
2704970 PSPICE SIMULATOR Incorrect bias point when VOFF is defined in curly braces for AC analysis
2818321 PSPICE SIMULATOR TOLERANCE ASSIGNED IN THE PSPICE MODEL IS NOT TRANSFERRED TO ASSIGN TOLERANCE FORM
470277 PSPICE SIMULATOR Node limitation for poly devices
2824674 PULSE CORE Issue on showing the number of USED SLOTS on Pulse dashboard.
2657425 PULSE DASHBOARD In Project Dashboard, sorting by date shows incorrect order
2774956 PULSE DASHBOARD Project Dashboard does not sort Date correctly.
2802915 PULSE DASHBOARD Pulse project dashboard sorts modified date by number rather than date
2879621 PULSE DASHBOARD Project Dashboard and the Open Projects takes longer time than expected in SPB 22.1
2903785 PULSE DASHBOARD Sorting by Modified date in the Pulse Project dashboard doesn’t look at the year.
2794509 PULSE LIVEBOM Unable to add a mechanical part to the selected variant Live BOM in System Capture.
2819794 PULSE LIVEBOM SPDWSRV-603 Error while accessing LiveBOM
2822338 PULSE LIVEBOM Incorrect condensed Live BOM Ref Des list
2828558 PULSE LIVEBOM Error (SPDWSRV-603): Unable to generate BOM because of an internal error
2813968 PULSE R2PLM-3DX-LIB Part relations to board models need to be pushed to 3DX in addition to footprint models
2801217 PULSE R2PLM-LIBSYNC Error while Configuring the New Part Request
2844225 PULSE R2PLM-TC Need ability to add mechanical parts without part reference in PFM output for PLM system BOM
2849670 PULSE R2PLM-WC WC classifications with display name attribute set to null cause errors in libsync
2766062 PULSE R2PLM The pfm utility needs to be able to handle generators that locate more than one output.
2766573 PULSE R2PLM Need to change "Published to" in the email response "Cadence Publish for Manufacturing Report"
2852085 SYSTEM_CAPTURE ADD_COMPONENT Split symbol can't be placed at the same location of another page
2889149 SYSTEM_CAPTURE ADD_COMPONENT Unable to place sequential split parts
2727760 SYSTEM_CAPTURE ARCHIVER Capability to Archive using GUI option
2786278 SYSTEM_CAPTURE ARCHIVER Enhancement Request for a GUI option for Archive design.
2858728 SYSTEM_CAPTURE AUTOMATION renameSignal command crashes syscap
2701676 SYSTEM_CAPTURE BOM Syscap variant bom_ignore variable request to be more versatile
2758195 SYSTEM_CAPTURE BOM Allow ability to set value of BOM_IGNORE property to something other than TRUE or FALSE
2759480 SYSTEM_CAPTURE BOM Need the ability to put in any value for the BOM_IGNORE property in System Capture.
2804432 SYSTEM_CAPTURE BOM Need the ability to put in any value for the BOM_IGNORE property in System Capture
2797465 SYSTEM_CAPTURE CONSTRAINT_MA When creating Xnets for mutil-section symbol it show some incorrect assignment of nets under Xnets
2853295 SYSTEM_CAPTURE CONSTRAINT_MA Creating Xnets for multi-section parts includes incorrect member nets under Xnets.
2760424 SYSTEM_CAPTURE COPY_PROJECT "Copy Project As" does not copy contents of physical directory.
2812600 SYSTEM_CAPTURE COPY_PROJECT System Capture, "Copy Project As" does not copy the physical folder.
2874375 SYSTEM_CAPTURE CRASHLOGGER Crash logger enhancement request to log more information
2847001 SYSTEM_CAPTURE EXPORT_PCB Room not created when set on hierarchical blocks in the design
2781868 SYSTEM_CAPTURE FIND_REPLACE Find and replace doesn't replace all net names, and creates mismatches between net names and physical names
2815425 SYSTEM_CAPTURE FIND_REPLACE Find and Replace with Selection enabled updates results beyond selection
2867920 SYSTEM_CAPTURE FIND_REPLACE Pasting a string from a CSV or XLSX file appends a space to the end of the pasted string
2731815 SYSTEM_CAPTURE FORMAT_OBJECT Renaming the power rail makes the net name visible
2861670 SYSTEM_CAPTURE GRID Electrical grid locked at the site can be changed at project by changing Documentation grid
2869735 SYSTEM_CAPTURE IMPORT_BLOCK DE-HDL design import - Net Names made invisible
2884645 SYSTEM_CAPTURE IMPORT_BLOCK CPLIB-2 error reported when 2 or more design imports are done during the same Syscap session
2857422 SYSTEM_CAPTURE IMPORT_DEHDL_ Error Message and avoid SysCap Crash
2881956 SYSTEM_CAPTURE IMPORT_DEHDL_ PB ASC Import Sheet(s) grid error message for some pages of DEHDL design
2706421 SYSTEM_CAPTURE IMPORT_PCB Enable gate swapping by default (ALLOW_HFS_SWAPS to ON by default)
2860720 SYSTEM_CAPTURE MISCELLANEOUS edif_300 output file is empty
2867334 SYSTEM_CAPTURE NAVLINKS TCL-Command navlinks -gen/-off does not change state of View > Navigation links
2856863 SYSTEM_CAPTURE NOTES Modify Note object placed on top of net
2798993 SYSTEM_CAPTURE PAGE_BORDER Unable to hide/unhide and add/remove properties attached to format or Page Border in System Capture.
2831793 SYSTEM_CAPTURE PART_MANAGER Unified Search can't place a part with space in cell name
2845010 SYSTEM_CAPTURE PART_MANAGER Loss of library contents corrupted an active schematic
2846046 SYSTEM_CAPTURE PART_MANAGER System Capture shows cache violations on components when design is opened in 22.1 ISR4
2859475 SYSTEM_CAPTURE PART_MANAGER Part Manager Update causes Synonyms to lose properties
2859519 SYSTEM_CAPTURE PERFORMANCE Opening pages takes too long in System Capture
2861063 SYSTEM_CAPTURE PERFORMANCE Performance improvement for generic editing options in System Capture
2861066 SYSTEM_CAPTURE PERFORMANCE Performing a undo operation on a group copy causes tool to hang
2616146 SYSTEM_CAPTURE PRINT System Capture: TOC overlaps watermarks
2901929 SYSTEM_CAPTURE PROJECT_EXPLO Fonts in Dropdown Menu are not as per font name in 23.1
2855245 SYSTEM_CAPTURE PROPERTY_EDIT When we select the component and try to change the visibility of prop using modifyprop, it do no work with list prop.
2549236 SYSTEM_CAPTURE REPLACE Net connections break after part replacement in System Capture.
2828259 SYSTEM_CAPTURE REPLACE Retain connectivity by matching pin location
2864163 SYSTEM_CAPTURE REPLACE Replace split part does not preserve the reference designator
2869144 SYSTEM_CAPTURE SHORTCUTS Syscap crashes at the time of launch with tcl file placed at site
2882901 SYSTEM_CAPTURE SMART_PDF PDF pin names are smaller when vertically oriented
2860187 SYSTEM_CAPTURE TABLE Import CSV file fails to bring the CSV contents if the design name has a hyphen or folder name has space
2836030 SYSTEM_CAPTURE TABLE_OF_CONT Tool takes a long time to open design with the TOC updates build
2845159 SYSTEM_CAPTURE TABLE_OF_CONT System Capture crashes during Find and Replace with TOC_AUTO_SAVE set to TRUE
2842356 SYSTEM_CAPTURE UI Inconsistent Symbol Menu for special symbols in System Capture
2841501 SYSTEM_CAPTURE UNIFIED_SEARC Filters loading in Unified Search takes 10 seconds for 28k parts
2855864 SYSTEM_CAPTURE UNIFIED_SEARC Syscap does not allow to make column visible in Unified search window
2883802 SYSTEM_CAPTURE UNIFIED_SEARC Getting SPPSUN-5 error while adding property header to Unified search.
2785940 SYSTEM_CAPTURE VARIANT_MANAG symbol is not having pin numbers in variant view
2872114 SYSTEM_CAPTURE VARIANT_MANAG Enable directive to skip jedec compatibility checks in Alt parts for variant flow in System Capture
2880027 SYSTEM_CAPTURE VARIANT_MANAG Disabling Show Cross on DNI does not work
2875747 SYSTEM_CAPTURE WIRING Adding inport to wire gives error: This operation leads to invalid connectivity.
2880370 SYSTEM_CAPTURE WIRING Moving wires created an extra wire
2843773 SYS_RELIABILITY STRESS_ANALYS Components connected to GND after EOS run
2851245 SYS_RELIABILITY STRESS_ANALYS PINUSE in Electrical Stress Setting changes depending on pin name
2860267 SYS_RELIABILITY STRESS_ANALYS Allow defining ferrite beads in Electrical Stress in Ohm or Henry
2867396 TOPXP OPTIMALITY_IN TOPXP-optimality Parallel Bus Bad eye diagrams are ignored when using BER eye height as objective function
2898050 TOPXP OPTIMALITY_IN TopWB Optimality Enhancement: Add measurement for Eye Aperture of All signal
2897054 TOPXP SSIVIEWER The min Jitter margin is shown as a negative value.
2752709 TOPXP SWEEP_MANAGER NMP(no measurement possible) in LPDDR5 report
2852801 TOPXP SWEEP_MANAGER Standby IO Model parameters are missing in sweep manager with SPB22.1 S005 build
2870428 TOPXP SWEEP_MANAGER Cannot sweep Standby IO model in Topology workbench in version SPB 22.1
2873475 TOPXP SYSTEMSI X1 defined in circuit ~~top has 11 nodes, subckt Tx1_SX4000 has 5 nodes.
2890620 TOPXP SYSTEMSI TdlVW/VdlVW values of DDR4-2400 differ with JEDEC’s Specifications
2898169 TOPXP SYSTEMSI Question about stimulus definition in Micron y32a.ibs on set to the controller block
CCRID Product ProductLevel2 Title
========================================================
2796563 ALLEGRO_EDITOR 3D_CANVAS 3D Rendering of layers appears incorrect.
2733652 ALLEGRO_EDITOR CROSS_SECTION In multi stackups mode All stackups tab is not showing all the stackups.
2796566 ALLEGRO_EDITOR CROSS_SECTION All Stackups tab does not show all stackups in the design.
2849582 ALLEGRO_EDITOR DATABASE Netlist import doesn't finish
2695403 ALLEGRO_EDITOR DFA DFA Placebound to Pastemask DRC
2773520 ALLEGRO_EDITOR DFA DFA Bubble not honoring multisided shape properly
2800298 ALLEGRO_EDITOR DFA DFA table is migrated to Constraint manager not showing DFA Bubble DRC during placement
2797313 ALLEGRO_EDITOR DFM Remove the legacy DFA table after migrating into the constraint manager DFA?
2856300 ALLEGRO_EDITOR DFM DFF Copper Spacing not picking up on via to shape of same net DRC
2848937 ALLEGRO_EDITOR EDIT_ETCH Cline bubble or hug around mechanical hole
2872449 ALLEGRO_EDITOR EDIT_ETCH Timing vision is bugged once "Enable Static Phase at Vias option" is enabled.
2593126 ALLEGRO_EDITOR GRAPHICS Shapes not highlighted when using "Reject" in GPU-mode (Linux).
2724555 ALLEGRO_EDITOR GRAPHICS SOV highlight displays odd behavior
2741223 ALLEGRO_EDITOR GRAPHICS Assign Color/Highlight Bundles in Allegro PCB Venture in 17.4 does not work with GPU enabled
2865769 ALLEGRO_EDITOR GRAPHICS Temp highlight behavior has no transparency
2872564 ALLEGRO_EDITOR GRAPHICS part of bundle flow not visible while in GPU mode
2867657 ALLEGRO_EDITOR IPC Enhancement to Output of drilled hole size and plating thickness to IPC-2581
2805884 ALLEGRO_EDITOR MCAD_COLLAB Shape subclass changing after importing IDF file
2853984 ALLEGRO_EDITOR MCAD_COLLAB IDX 4.0 import issue with Onshape tool
2880362 ALLEGRO_EDITOR MCAD_COLLAB IDF Import on Flex design with zone using Multi cross-section swaps symbols shapes incorrectly
2810059 ALLEGRO_EDITOR SHAPE Thermal ties not as expected
2838112 ALLEGRO_EDITOR UI_GENERAL Paste not working in telskill window
2863683 ALLEGRO_EDITOR UI_GENERAL axlUIMultipleChoice - giving wrong return value upon escape/cancel
2865778 ALLEGRO_EDITOR UI_GENERAL Include user env setting to auto clear search string in find by name textbox when enter is pressed
2866911 ALLEGRO_EDITOR UI_GENERAL “Paste” does not work in the SKILL (set telskill) window (SPB22.1 HF6)
2865644 ALLEGRO_EDITOR VIA_STRUCTURE Issue with eXML file generation for high-speed via structure in Allegro
2700354 APD ASSY_RULE_CHE Degassing void overlap issue
2713336 APD ASSY_RULE_CHE Slow performance with void-void spacing
2867235 APD ASSY_RULE_CHE Assembly rule checker is taking too long to run
2831000 APD DEGASSING Create a new SKILL API for the equivalant to erase Adv Degassing holes
2833487 APD DEGASSING APD tool is crashing when doing degassing>shape update
2867204 APD DEGASSING Advanced shape degassing is crashing APD+
2876179 APD INTERACTIVE Netin crashes on the attached design
2903349 APD IN_DESIGN_ANA About the display of System Configuration Editor
2872861 APD MULTI_USER Symphony rejection issues when deleting vias
2851011 APD STREAM_IF Suppress unconnected pads option and Stream Out
2867199 APD STREAM_IF Missing degassing holes on GDS file
2877139 APD STREAM_IF Pad Degassing not showing correctly in the stream out file
2854817 ASI_SI GUI Unable to set material properties for solderbump and ball in APD for XIM extraction
2790801 CONCEPT_HDL CORE When I try to mark a top level block instance as DNI in the variant schematic view. ConcptHDL crashes..
2831459 CONCEPT_HDL CORE space at the beginning of the sentence is deleted.
2848319 CONCEPT_HDL CORE Cadence HDL 22.1 ISR 005 - Crash
2850517 CONCEPT_HDL CORE Why is net PWR_CNT not in net group HV_GRP1 in the constraint manager. It has that net_group attribute on the net. It wa
2793171 CONCEPT_HDL OTHER Variant editor and marking components as variants and DNI causing DEHDL to crash
2844121 CONCEPT_HDL OTHER Process gets stuck with 22.1 while running tcl commands
2864910 CONSTRAINT_MGR SYSCAP NetClass shows stale members when using SKILL API to query members
2893851 PCB_LIBRARIAN LIBDB_CORE "BPC23_LIB" Pin length is not suitable from "Add pin" button
2858871 PCB_LIBRARIAN SYMBOL_EDITOR Support Allegro System Capture to OrCAD Capture translation for zero-length pin stubs.
2762447 PCB_LIBRARIAN SYMBOL_EDITOR Cant change documentation grid in NSE
2820516 PCB_LIBRARIAN SYMBOL_EDITOR Documentation grid is incorrect in NSE
2807043 PCB_LIBRARIAN SYM_CREATOR_C Executing expand vector pin is slow in new Symbol Editor
2807073 PCB_LIBRARIAN SYM_CREATOR_C The move command is slow for pin numbers in new Symbol Editor
2102930 PSPICE AA_MC PSpice AA Monte Carlo slow compared to standard MC
2195199 PSPICE AA_MC Advanced Analysis Monte Carlo performance is slow as compared to standard MC
2781887 PSPICE AA_MC Enhancement for speed improvement of PSpiceAA MC runs.
2841035 PSPICE AA_MC PSpice AA MC is significantly slower than PSpice MC
2841038 PSPICE AA_MC PSpice AA MC is significantly slower than PSpice MC
2893141 PSPICE ENVIRONMENT Unable to launch PSpice Basic version with license ALG200
1375245 PSPICE MODELEDITOR Improve error message while saving file if backup directory is read only
2179166 PSPICE NETLISTER PSpice Netlist Error but nothing in Session Log for attached testcase
1188042 PSPICE SIMULATOR INTERNAL ERROR – Overflow Convert
2191276 PSPICE SIMULATOR Inconsistent bias point results with Vpulse source.
2238626 PSPICE SIMULATOR Tolerance of BJT's param from model is not taken account in PSpice Advanced Analysis v17.4 Assign Tolerance
2243592 PSPICE SIMULATOR Long .param statement in .include file NOT included, with no warning or error.
2657100 PSPICE SIMULATOR PSpice Monte Carlo error "Illegal parameter value in input file"
2704970 PSPICE SIMULATOR Incorrect bias point when VOFF is defined in curly braces for AC analysis
2818321 PSPICE SIMULATOR TOLERANCE ASSIGNED IN THE PSPICE MODEL IS NOT TRANSFERRED TO ASSIGN TOLERANCE FORM
470277 PSPICE SIMULATOR Node limitation for poly devices
2824674 PULSE CORE Issue on showing the number of USED SLOTS on Pulse dashboard.
2657425 PULSE DASHBOARD In Project Dashboard, sorting by date shows incorrect order
2774956 PULSE DASHBOARD Project Dashboard does not sort Date correctly.
2802915 PULSE DASHBOARD Pulse project dashboard sorts modified date by number rather than date
2879621 PULSE DASHBOARD Project Dashboard and the Open Projects takes longer time than expected in SPB 22.1
2903785 PULSE DASHBOARD Sorting by Modified date in the Pulse Project dashboard doesn’t look at the year.
2794509 PULSE LIVEBOM Unable to add a mechanical part to the selected variant Live BOM in System Capture.
2819794 PULSE LIVEBOM SPDWSRV-603 Error while accessing LiveBOM
2822338 PULSE LIVEBOM Incorrect condensed Live BOM Ref Des list
2828558 PULSE LIVEBOM Error (SPDWSRV-603): Unable to generate BOM because of an internal error
2813968 PULSE R2PLM-3DX-LIB Part relations to board models need to be pushed to 3DX in addition to footprint models
2801217 PULSE R2PLM-LIBSYNC Error while Configuring the New Part Request
2844225 PULSE R2PLM-TC Need ability to add mechanical parts without part reference in PFM output for PLM system BOM
2849670 PULSE R2PLM-WC WC classifications with display name attribute set to null cause errors in libsync
2766062 PULSE R2PLM The pfm utility needs to be able to handle generators that locate more than one output.
2766573 PULSE R2PLM Need to change "Published to" in the email response "Cadence Publish for Manufacturing Report"
2852085 SYSTEM_CAPTURE ADD_COMPONENT Split symbol can't be placed at the same location of another page
2889149 SYSTEM_CAPTURE ADD_COMPONENT Unable to place sequential split parts
2727760 SYSTEM_CAPTURE ARCHIVER Capability to Archive using GUI option
2786278 SYSTEM_CAPTURE ARCHIVER Enhancement Request for a GUI option for Archive design.
2858728 SYSTEM_CAPTURE AUTOMATION renameSignal command crashes syscap
2701676 SYSTEM_CAPTURE BOM Syscap variant bom_ignore variable request to be more versatile
2758195 SYSTEM_CAPTURE BOM Allow ability to set value of BOM_IGNORE property to something other than TRUE or FALSE
2759480 SYSTEM_CAPTURE BOM Need the ability to put in any value for the BOM_IGNORE property in System Capture.
2804432 SYSTEM_CAPTURE BOM Need the ability to put in any value for the BOM_IGNORE property in System Capture
2797465 SYSTEM_CAPTURE CONSTRAINT_MA When creating Xnets for mutil-section symbol it show some incorrect assignment of nets under Xnets
2853295 SYSTEM_CAPTURE CONSTRAINT_MA Creating Xnets for multi-section parts includes incorrect member nets under Xnets.
2760424 SYSTEM_CAPTURE COPY_PROJECT "Copy Project As" does not copy contents of physical directory.
2812600 SYSTEM_CAPTURE COPY_PROJECT System Capture, "Copy Project As" does not copy the physical folder.
2874375 SYSTEM_CAPTURE CRASHLOGGER Crash logger enhancement request to log more information
2847001 SYSTEM_CAPTURE EXPORT_PCB Room not created when set on hierarchical blocks in the design
2781868 SYSTEM_CAPTURE FIND_REPLACE Find and replace doesn't replace all net names, and creates mismatches between net names and physical names
2815425 SYSTEM_CAPTURE FIND_REPLACE Find and Replace with Selection enabled updates results beyond selection
2867920 SYSTEM_CAPTURE FIND_REPLACE Pasting a string from a CSV or XLSX file appends a space to the end of the pasted string
2731815 SYSTEM_CAPTURE FORMAT_OBJECT Renaming the power rail makes the net name visible
2861670 SYSTEM_CAPTURE GRID Electrical grid locked at the site can be changed at project by changing Documentation grid
2869735 SYSTEM_CAPTURE IMPORT_BLOCK DE-HDL design import - Net Names made invisible
2884645 SYSTEM_CAPTURE IMPORT_BLOCK CPLIB-2 error reported when 2 or more design imports are done during the same Syscap session
2857422 SYSTEM_CAPTURE IMPORT_DEHDL_ Error Message and avoid SysCap Crash
2881956 SYSTEM_CAPTURE IMPORT_DEHDL_ PB ASC Import Sheet(s) grid error message for some pages of DEHDL design
2706421 SYSTEM_CAPTURE IMPORT_PCB Enable gate swapping by default (ALLOW_HFS_SWAPS to ON by default)
2860720 SYSTEM_CAPTURE MISCELLANEOUS edif_300 output file is empty
2867334 SYSTEM_CAPTURE NAVLINKS TCL-Command navlinks -gen/-off does not change state of View > Navigation links
2856863 SYSTEM_CAPTURE NOTES Modify Note object placed on top of net
2798993 SYSTEM_CAPTURE PAGE_BORDER Unable to hide/unhide and add/remove properties attached to format or Page Border in System Capture.
2831793 SYSTEM_CAPTURE PART_MANAGER Unified Search can't place a part with space in cell name
2845010 SYSTEM_CAPTURE PART_MANAGER Loss of library contents corrupted an active schematic
2846046 SYSTEM_CAPTURE PART_MANAGER System Capture shows cache violations on components when design is opened in 22.1 ISR4
2859475 SYSTEM_CAPTURE PART_MANAGER Part Manager Update causes Synonyms to lose properties
2859519 SYSTEM_CAPTURE PERFORMANCE Opening pages takes too long in System Capture
2861063 SYSTEM_CAPTURE PERFORMANCE Performance improvement for generic editing options in System Capture
2861066 SYSTEM_CAPTURE PERFORMANCE Performing a undo operation on a group copy causes tool to hang
2616146 SYSTEM_CAPTURE PRINT System Capture: TOC overlaps watermarks
2901929 SYSTEM_CAPTURE PROJECT_EXPLO Fonts in Dropdown Menu are not as per font name in 23.1
2855245 SYSTEM_CAPTURE PROPERTY_EDIT When we select the component and try to change the visibility of prop using modifyprop, it do no work with list prop.
2549236 SYSTEM_CAPTURE REPLACE Net connections break after part replacement in System Capture.
2828259 SYSTEM_CAPTURE REPLACE Retain connectivity by matching pin location
2864163 SYSTEM_CAPTURE REPLACE Replace split part does not preserve the reference designator
2869144 SYSTEM_CAPTURE SHORTCUTS Syscap crashes at the time of launch with tcl file placed at site
2882901 SYSTEM_CAPTURE SMART_PDF PDF pin names are smaller when vertically oriented
2860187 SYSTEM_CAPTURE TABLE Import CSV file fails to bring the CSV contents if the design name has a hyphen or folder name has space
2836030 SYSTEM_CAPTURE TABLE_OF_CONT Tool takes a long time to open design with the TOC updates build
2845159 SYSTEM_CAPTURE TABLE_OF_CONT System Capture crashes during Find and Replace with TOC_AUTO_SAVE set to TRUE
2842356 SYSTEM_CAPTURE UI Inconsistent Symbol Menu for special symbols in System Capture
2841501 SYSTEM_CAPTURE UNIFIED_SEARC Filters loading in Unified Search takes 10 seconds for 28k parts
2855864 SYSTEM_CAPTURE UNIFIED_SEARC Syscap does not allow to make column visible in Unified search window
2883802 SYSTEM_CAPTURE UNIFIED_SEARC Getting SPPSUN-5 error while adding property header to Unified search.
2785940 SYSTEM_CAPTURE VARIANT_MANAG symbol is not having pin numbers in variant view
2872114 SYSTEM_CAPTURE VARIANT_MANAG Enable directive to skip jedec compatibility checks in Alt parts for variant flow in System Capture
2880027 SYSTEM_CAPTURE VARIANT_MANAG Disabling Show Cross on DNI does not work
2875747 SYSTEM_CAPTURE WIRING Adding inport to wire gives error: This operation leads to invalid connectivity.
2880370 SYSTEM_CAPTURE WIRING Moving wires created an extra wire
2843773 SYS_RELIABILITY STRESS_ANALYS Components connected to GND after EOS run
2851245 SYS_RELIABILITY STRESS_ANALYS PINUSE in Electrical Stress Setting changes depending on pin name
2860267 SYS_RELIABILITY STRESS_ANALYS Allow defining ferrite beads in Electrical Stress in Ohm or Henry
2867396 TOPXP OPTIMALITY_IN TOPXP-optimality Parallel Bus Bad eye diagrams are ignored when using BER eye height as objective function
2898050 TOPXP OPTIMALITY_IN TopWB Optimality Enhancement: Add measurement for Eye Aperture of All signal
2897054 TOPXP SSIVIEWER The min Jitter margin is shown as a negative value.
2752709 TOPXP SWEEP_MANAGER NMP(no measurement possible) in LPDDR5 report
2852801 TOPXP SWEEP_MANAGER Standby IO Model parameters are missing in sweep manager with SPB22.1 S005 build
2870428 TOPXP SWEEP_MANAGER Cannot sweep Standby IO model in Topology workbench in version SPB 22.1
2873475 TOPXP SYSTEMSI X1 defined in circuit ~~top has 11 nodes, subckt Tx1_SX4000 has 5 nodes.
2890620 TOPXP SYSTEMSI TdlVW/VdlVW values of DDR4-2400 differ with JEDEC’s Specifications
2898169 TOPXP SYSTEMSI Question about stimulus definition in Micron y32a.ibs on set to the controller block
Cadence OrCAD X Platform 2023 (23.10.001)
Cadence OrCAD X Platform 2023 (23.10.001)
Cadence OrCAD X Platform 2023 (23.10.001)
OrCAD X is an innovative design platform that caters to the needs of individuals and small to midsize businesses. It focuses on providing a cohesive and comprehensive solution for all design requirements. The addition of the X in this new product platform signifies its ability to extend its capabilities to the Cloud, enabling users to leverage additional services like X AI.
OrCAD X Presto, a new layout environment within the OrCAD X platform, offers a cuttingedge solution for layout design. The interoperability between OrCAD X Presto and the existing PCB Editor ensures compatibility and easy transition of layout designs. OrCAD X Presto can be used in Cloud-connected and unconnected modes, allowing you to work flexibly based on your preferences and requirements. OrCAD X Presto elevates the user experience by eliminating the need for modal dialog boxes. Instead, layout toolbars and floating menus are implemented, reducing distractions and ensuring the design space is always unblocked and accessible. This architecture significantly enhances productivity and allows designers to focus on their work. OrCAD X Presto includes an integrated 3D viewer that seamlessly switches between 2D and 3D views. This feature enables designers to perform fast and accurate 3D analysis, supporting 3D clearance Design Rule Checks (DRCs). This integration enhances visualization capabilities, allowing the designers to identify and address potential manufacturing issues quickly and efficiently
OrCAD X
Learn about the OrCAD X Platform and see how it's capabilities and easy to use interface help you design fast, correct and connected.
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For.
Owner: Cadence
Product Name: OrCAD X Platform
Version: 2023 (23.10.001)
Supported Architectures: x64
Website Home Page : www.cadence.com
Languages Supported: english
System Requirements: Windows *
Size: 12.6 Gb
Cadence SPB OrCAD X / Allegro X 2023 (23.10.000)
Cadence SPB OrCAD X / Allegro X 2023 (23.10.001) Hotfix
Orcad LibraryBuilder 2023 (23.1.1)
Cadence SPB OrCAD X / Allegro X 2023 (23.10.001) Hotfix
Orcad LibraryBuilder 2023 (23.1.1)
Cadence OrCAD X Platform 2023 (23.10.001)
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Added by 3% of the overall size of the archive of information for the restoration
No mirrors please
Cadence OrCAD X Platform 2023 (23.10.001)
