Cadence XCELIUM version 23.03.001

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CCRID Product Title
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AVSREQ-165518 DMS_LP_AMS Support xrun option -lps_ams_1801_analog_ccnd in UPF (similar to CPF)
AVSREQ-179180 VWDB Merge to Xcelium 22.09 fix for VWDB-4216 and VWDB-4221
AVSREQ-172980 VHDL_GENERAL VHDL predefined attribute 'subtype not supported
AVSREQ-176719 SV_PERFORMANCE xrio degradation 1.28x compare to RTL
AVSREQ-178025 SYSC_COMPILER xmsc is not creating all rules in Makefile.xmsc
AVSREQ-178735 GLS_SDF Simulation crashing with SDF annotation
AVSREQ-167929 COVERAGE_COVERGROUP Support of Covergroup in CU scope
AVSREQ-184499 SIM_SV Simulation misbehavior with -enable_unpkd_index_aa
AVSREQ-185288 SIM_PERFORMANCE elaboration exits when not using -disable_var_opt_core
AVSREQ-176408 IP_PROTECT_GENERAL xmprotect to be able to encrypt a gate-level netlist (.vg from vhelab) that includes a mix of encrypted and unencrypted RTL content
AVSREQ-176281 GLS_PERFORMANCE Different simulation behavior in 22.03.v002 and 21.09.v007
AVSREQ-181752 LP_LIBERTY xmlib2cdb -v results in error in 22.03
AVSREQ-185340 PARSE_SV Unexpected *W,NOUNAD in GREEN rebase (22.12.a071)
AVSREQ-176661 SPECTRE_AMSD Elaborator picks wrong SPECTRE subckt definition for SPICE on top configuration
AVSREQ-174387 ELAB_SV xmelab: *F,INTERR: INTERNAL EXCEPTION with MESSAGE: sv_seghandler - trapno -1 addr(0x12)
AVSREQ-177032 DMS_AMSD Add error for duplicate ports : (causes simulation crash: gq_isforceassign - illegal class)
AVSREQ-178376 SIM_SV xmsim: *F,INTERR with svh_deref - h out of bounds when using -classlinedebug
AVSREQ-179416 SV_INTERFACE xmelab crash with backtrace: cu_vifc_normalize_portal_list.isra.0
AVSREQ-183106 SPECMAN_E Simvision GUI crashes in Specman with Xcelium 22.09.s002 version
AVSREQ-176507 LP_LIBERTY Enable xmlib2cdb to read cds.lib to place the index file in
AVSREQ-177143 SPECTRE_AMSD Unable to plot analog signal with default rawfmt (udb / psfxl) in Simvision
AVSREQ-185010 MSIE_ELAB Incorrect runme and incremental verilog config file dumped in genmsiedata flow
AVSREQ-151648 VHDL_CODEGEN VHDL_cg does not work
AVSREQ-183390 LP_SIM_PERF flop updated without clk trigger
AVSREQ-177930 SPECMAN_COV OS signal 11 (segmentation violation) received
AVSREQ-180934 MSIE_PERFORMANCE Umbrella options needed for MSIE
AVSREQ-179923 SIM_PERFORMANCE xmvlog_cg: *F,INTERR: INTERNAL EXCEPTION with "gq_e_relational_integral - BWL width mismatch"
AVSREQ-180455 DMS_CONNECT_MOD timescale directives missing on all three EEnet_2_E IEs in the xcelium connect_lib
AVSREQ-182263 RAND_SOLVER Change default behavior for implicit constraints on enums in unions
AVSREQ-148427 SV_GENERAL Support of sparse array (-sparsearray) for the multidimensional unpacked array
AVSREQ-127505 XPESSIMISM_GENERAL XPESS: Need method to provide multiple xpess scopes
AVSREQ-169274 SV_BUILD_PERF ENABLE_CLASS_SPECIALIZATION_OPT degrades MSIE build time
AVSREQ-124645 VHDL_GENERAL VHDL-2008 support is broken because of reliance on non-standard "std_logic_1164_additions" package
AVSREQ-178193 RAND_SOLVER Randomization fails on 22.09
AVSREQ-185002 LP_ISOLATION LPPNCH message needs to provide more info
AVSREQ-169414 MSIE_PERFORMANCE Provide a warning when top level module is defined as primtop without any lower/adjacent incrtop/top
AVSREQ-177141 LP_1801 Enhancement required to allow set_port_attribute -ports and -elements {.} together
AVSREQ-179194 DEBUG_PROBE Support multiple selective class member probes
AVSREQ-144378 SV_GENERAL Sparsearray option to work for multi-dimensional unpacked array as well
AVSREQ-177517 ELAB_CLONE Add an option -exclude_xmclone_top to exclude any partition in xmclone
AVSREQ-180620 PARSE_SV Compile error: xmvlog: *E,ILLPRI
AVSREQ-183535 JUPITER_GL_SC track checkins for AVSREQ-175812
AVSREQ-174518 VHDL_GENERAL VHDL 2008 Construct
AVSREQ-155729 PARSE_SV Can Xcelium ignore check for no used library file ?
AVSREQ-153275 LP_DOC UPF documentation requires an update about -Simstate
AVSREQ-185143 LP_RETENTION Break sub-strategies by reset/clock pairs even when UPF_GENERIC_ASYNC_LOAD is not used
AVSREQ-156224 COVERAGE_CODE Need help understanding expression table entries and why it is shown as not covered
AVSREQ-180448 SPECTRE_AMSD Enhance connect modules to allow different delay for a rising and a falling edge
AVSREQ-101005 DMS_LP_AMS WCNDNWR error when -lps_cov option is used
AVSREQ-177051 SV_DATATYPES xmsim crash with sv_seghandler - trapno -1 addr(0x14)
AVSREQ-177349 SPECTRE_AMSD Invalid value returned by value -flow (run -sync)
AVSREQ-175817 SIM_PERFORMANCE wire value not updated; running with default access permissions
AVSREQ-177967 MSIE_ELAB Internal exception after version up
AVSREQ-183590 SV_PERFORMANCE xmsim: *F,INTERR: INTERNAL EXCEPTION : Traceback (most recent call last): File "/home/tools/cadence/XCELIUM22.08_e485/tools/bin/stackwalk.py", line 293, in <module> stack_walk()
AVSREQ-166812 SV_GENERAL Force value not relayed to upper hierarchies
AVSREQ-174803 COVERAGE_COVERGROUP Wrong error pointed by tool during parsing
AVSREQ-186007 DMS_SIM Using $dumpvars on UDN leads to an Internal Exception
AVSREQ-177029 PARSE_SV *E,ASRTST: Assertion failure
AVSREQ-177067 MSIE_ELAB MSIE genhref flow causing unexpected behavior during incremental build
AVSREQ-179396 VPI_GENERAL VPI issue in interactive: ref class handle is null although it is not
AVSREQ-180440 XPROPAGATION_PERFORMANCE Wrong RTSVAV message is being issued with enable_xp_nba_perf option
AVSREQ-98171 SV_DATATYPES ref event in task does not work
AVSREQ-181251 RAND_SOLVER Randomize performance issue
AVSREQ-180171 VST_PRIME -xform_lite For_generate_assign_01 causing WANOTL error
AVSREQ-159407 RAND_GENERAL Simulator Crash with the following error: vsto_op_pdata - PARAMETER - no value, class 745
AVSREQ-168087 SIM_FORCE_RELEASE ssslib snare action function, consuming more than 73% time in GLST setup. No wave dump enabled
AVSREQ-177458 LP_SIM_PERF xmsim: *F,INTERR: INTERNAL EXCEPTION in the middle of simulation
AVSREQ-175047 SV_GENERAL *E,STRCAT: this item is not assignment-compatible with 'string', yet it is in a concatenation that includes another item with the datatype 'string'.
AVSREQ-184022 SIM_PERFORMANCE xmelab time degrades w.r.t 21.07, long time in gwm_cleanup
AVSREQ-180233 ELAB_SV xmelab MESSAGE: sv_seghandler - trapno -1 addr(0x7ffe42fd1ff8)
AVSREQ-163907 LP_1801 Please provide support for "is_pad" of liberty file.
AVSREQ-187233 RAND_SOLVER Solver crash on misuse of reduction function on 2d array
AVSREQ-180578 POWERPLAYBACK_GENERAL Adjust Presim time from 0 to fix power switch chain cause X value when signal exist in mapping file
AVSREQ-177687 FUNC_SAFETY_CONCURRENT MESSAGE: sv_seghandler - trapno -1 addr(0x1a)
AVSREQ-183729 ASSERTION_SIM SmartLog missing ASRTST
AVSREQ-173822 ASSERTION_SIM Tool crashes during sim restart with probes in input TCL file
AVSREQ-179666 FUNC_SAFETY_CONCURRENT MESSAGE: vst_class() - not in range: 80
AVSREQ-175900 ELAB_CLONE superunit crashes with xmclone2 and xmclone_memopt
AVSREQ-181148 ELAB_CLONE smm_protect() - unable to protect, 'Cannot allocate memory'
AVSREQ-164718 PARSE_SV Display of hierarchically described definitions
AVSREQ-184926 LP_1801 unclear elab error INVPFL message
AVSREQ-178567 PARSE_SV Function Chaining error with find_index method on Queue
AVSREQ-179706 RAND_SOLVER no distribution report for multiple conditional dist constraint
AVSREQ-184985 DEBUG_DESIGN_DATABASE Customer failed to trace drivers from Class which is included under module definition
AVSREQ-182455 GLS_SDF EHF(22.10-e594-20221013) version has elaboration performance degrade
AVSREQ-179682 FUNC_SAFETY_CONCURRENT MESSAGE: sv_seghandler - trapno -1 addr(0xfffffffffffffff8)
AVSREQ-180094 ELAB_SV JSON file is not generated with -enable_custom_format_system_tasks and -JSON_FILE_PATH
AVSREQ-166099 ELAB_BIND CPF simulation : auto generated cds_amslps_psnconn_ams not found during elaborating design hierarchy
AVSREQ-180526 PARSE_SV Internal exception error after changing the tool version from 22.07 to 22.09.a071 or 22.10.a071
AVSREQ-181743 VPI_GENERAL Incorrect object returned for textRef to a ref object in UVM
AVSREQ-170759 RAND_GENERAL crash smi_get_source_marker with seed_trace in fork.join_none
AVSREQ-176844 SIM_VHPI Support for VHPI to work in uVisa mode with OT's for array range utilities
AVSREQ-175414 VHDL_CODEGEN tool crash with in function with return of record types in vhdl
AVSREQ-176353 PARSE_SV False error xmelab NUMARG even when all arguments to a task are passed
AVSREQ-182119 GLS_SDF Internal exception when elaborating netlist + SDF
AVSREQ-181151 SPECTRE_AMSD dna_assembler always prints message saying using an old version of Spectre
AVSREQ-175962 LP_LIBERTY Xcelium elab unable to instrument liberty info from cdb to the HDL in low power build
AVSREQ-178259 LP_1801 force does not reapply in upf sim
AVSREQ-181150 LP_LIBERTY Suppressing error messages not related to LP Sim while generating ".cdb" by using xmlib2cdb
AVSREQ-177225 ELAB_SV xmelab still attempts file locking when -nolock is used
AVSREQ-178632 PROBE Multi-dimensional associative array cannot be probed
AVSREQ-163490 DMS_ELAB Systemverilog interface modport not supported with analog signals
AVSREQ-183099 LP_CLONE xmclone does not work properly on LP design (qbicair)
AVSREQ-178691 ASSERTION_PERFORMANCE Elab Crash with cu_xmark_called_processes_flushing
AVSREQ-171855 MSIE_SIMULATION MSIE: Issue in TCL force resulting in crash at gate primitive
AVSREQ-174306 LP_1801 Retention strategy is not being broken down into unique clock and reset groupings.
AVSREQ-179392 LP_SV const SV struct gets corrupted
AVSREQ-179179 SV_PORTS Need extend support for *E,PCRFNC
AVSREQ-178178 VSP_SIMULATION Exception error/crash while dumping the Profile report in NBRUN mode
AVSREQ-179013 SPECTRE_AMSD memory leak in AMS
AVSREQ-99834 XRUN_GENERAL Passing +coverage from command line on irun
AVSREQ-176932 ELAB_BIND VCONFIG: Setting parameters in config block
AVSREQ-177929 PARSE_SV xmdc decompiled code produces FNDKWD compile error on recompiling.
AVSREQ-156451 SV_PARAMETERS NOTDOT: Hierarchical Name in a Constant Expression in a For Generate
AVSREQ-185539 ASSERTION_SVA xmvlog INTERR: ebs_dump_ncyc_hdl
AVSREQ-184358 DEBUG_DESIGN_DATABASE Driver tracing fail to follow a modport signal which is inside a nested generate
AVSREQ-185165 FUNC_SAFETY_CONCURRENT Exit during fault injection
AVSREQ-179087 ELAB_BIND Hierarchical path is inaccessible when an virtual interface is instantiated through bind
AVSREQ-178406 SIM_PERFORMANCE Elaboration crash with tl_find_master_always - master not found message.
AVSREQ-180004 SV_DATATYPES SVNIMP error on initialization of an int struct member
AVSREQ-183663 GLS_SDF Internal Exception during simulation
AVSREQ-179094 ASSERTION_PERFORMANCE test hang on an assertion in 22.09.v not 21.09.v7
AVSREQ-171680 ASSERTION_SIM Show assertion result at end of simulation
AVSREQ-186980 DEBUG_DESIGN_DATABASE Source code is unreadable when running with gzipped file
AVSREQ-184277 RAND_DEBUG Mix old Xcelium with new librnc cause assertion failure when using utrace/indago
AVSREQ-181933 ASSERTION_SIM xmprof - Assertion Summary Counts clearification
AVSREQ-182320 ELAB_PERF Multi-Xrun MSIE flow: TYCMPAT error with enable_class_specialization_opt
AVSREQ-182941 DEBUG_DESIGN_DATABASE VHDL driver tracing stops in generate block (Schematics)
AVSREQ-181143 ASSERTION_PERFORMANCE assertion tcl multi line with one line with PNOOBJ error
AVSREQ-176502 ELAB_PERF Crash on 12th Aug nightly agile with -enable_portbit_select_opt: 3rd Aug nightly agile works fine
AVSREQ-180509 SIMVISION_GENERAL SIMVISION: Export to VCD generates wrong name when for expressions with no name
AVSREQ-181216 COVERAGE_COVERGROUP CUVBVE Warning when binding coverage module
AVSREQ-177871 FUNC_SAFETY_CONCURRENT Support -select_top_cell_only with -select_ports
AVSREQ-107505 LP_1801 -lps_logfile lps.log is appending log file on each run and not over writing
AVSREQ-180896 POWERPLAYBACK_GENERAL Add a new internal PowerPlayback configuration switch to enable dumping at time=0
AVSREQ-180751 PARSE_SV Support for "events" in -vlogcontrolrelax switch
AVSREQ-176659 ELAB_CLONE INTERNAL EXCEPTION with MESSAGE: vst_identifier () - bad class, class 739
AVSREQ-180090 RAND_GENERAL std::randomize is not honoring a constraint
AVSREQ-182283 LP_1801 Xcelium overwrite UPF version
AVSREQ-175014 LP_VHDL sequential process resumed on power up
AVSREQ-176461 COVERAGE_ASSERTIONS Selecting functional coverage for a specific module does not work when using -assertion and -corvergroup
AVSREQ-179451 SIM_SAIF_TCF Reduce SAIF file information (Master CCR)
AVSREQ-162896 RAND_SOLVER RNDCNSTE Randomization constraint error
AVSREQ-180791 LP_BUILD_PERF reduce time in checkpoint pwrImAssertControl
AVSREQ-184735 SIM_SAIF_TCF Pending issues from AVSREQ-179451 (Reduce SAIF file information)
AVSREQ-177705 SV_PARAMETERS xmelab INTERR sv_seghandler when automatic function passed localparam that matches input size declared
AVSREQ-145599 SPECMAN_GENERAL otf_threshold should be updated according to optimal_process_size value
AVSREQ-164929 DMS_ELAB Restrict number of logfile lines when running Coercion Debug on a net deep in a design hierarchy
AVSREQ-180583 SIM_SV Displaying simulation time in SIGCOL and SIGNOC messages.
AVSREQ-181716 MSIE_ELAB Automate the dumping and consumption of defparam in msiedata flow
AVSREQ-100910 DMS_LP_AMS Internal Exception during CPF run with PMC IP in spice
AVSREQ-181877 LP_1801 Xcelium low-power static log file missing some upf files.
AVSREQ-176433 SIM_PERFORMANCE Performance enhance request #1 for Modem IP
AVSREQ-179707 RAND_SOLVER No check for some dist variables due to nested conditional dist constraints
AVSREQ-181321 MSIE_ELAB HREFAC messages in single-step MSIE and re-elaboration of primaries
AVSREQ-179245 DEBUG_DESIGN_DATABASE Need assist to debug hard to reproduce DLCOIF error
AVSREQ-175938 SAVE_RESTART_GENERAL Save Restart flow; failure in trying to find the saved dir after relocating it
AVSREQ-178911 SIM_USABILITY error message when simlogsize is reached is not parsable
AVSREQ-177041 XPROPAGATION_GENERAL Combination of xprop and access r causes infinite loop
AVSREQ-122847 GLS_TIMING tcheck usage wrong in user guide
AVSREQ-179890 SIM_PERFORMANCE incremental elab. crash, MESSAGE: dta_notify_register - bad input kind
AVSREQ-179556 SV_PERFORMANCE Event missing in for-loop in generate block
AVSREQ-186481 GLS_SDF Elab crashed with "acg_merge_nodes: parent/child link inconsistent!"
AVSREQ-170509 SAVE_RESTART_GENERAL restart of a saved image fails with dump
AVSREQ-180173 LP_BUILD_PERF reduce time in checkpoint pwrImAssertControl
AVSREQ-180581 SPECMAN_COV False warning for a ungradable item that is under no_collect
AVSREQ-171458 ELAB_CLONE XMELAB internal error with XMCLONE - nettmp_fetch_id - id 5050458 is out of range
AVSREQ-177688 ELAB_PERF xmclone_min_pct 0.00015625 causes crash MESSAGE: smm_protect() - unable to protect, 0x2b194a3f0080 0x2b194a3f0000 262208 266240 3 'Cannot allocate memory'
AVSREQ-183109 RAND_SOLVER incorrect SystemVerilog constraint solver error
AVSREQ-177626 PARSE_SV xmvlog hangs in vlog/directives.c
AVSREQ-177766 SR_BACKDOOR SR_backdoor: Discrepancy in variable field of the trace file
AVSREQ-175458 SV_PARAMETERS Internal error "vxt_read_obj - !pib/VST_D_REG" when -VLOGCONTROLRELAX NOTPAR is present
AVSREQ-177161 XRUN_SYSC Enhancement xrun option to instruct it to invoke the C compiler to create a librun.so : option -create_sharedlib
AVSREQ-176593 SV_CLASSES xmelab crash with cu_xrenumber_tablet message in GREEN 21.09-v007
AVSREQ-147245 PARSE_SV xmvlog: *E, FEWCAA
AVSREQ-178726 LP_LIBERTY cdbver message created when icdb file is used
AVSREQ-183130 LP_1801 xmelab crash with 22.12 agile
AVSREQ-171116 MSIE_SIMULATION Slower runtime with MSIE flow
AVSREQ-181161 GLS_GENERAL GLS - To print the net names whenever glitches occurs in the log file based on the user choice
AVSREQ-179995 RAND_GENERAL xmsim: *F,RNDUNR: XCELIGEN assertion failed - is_logic_expr()
AVSREQ-179395 SIM_SV xmsim crash w/ FSDB dump using cosim environment w/ EHF provided for xmsim w/ -FPIC
AVSREQ-170521 SV_CODEGEN Code generation intermittently fails with *E,MCVCGF error when "-mccodegen" option is used.
AVSREQ-179983 SIM_PERFORMANCE Elab crash blocking MBIST IP migrations
AVSREQ-177682 SV_CODEGEN newperf switch is causing a crash
AVSREQ-171783 SV_CODEGEN xmvlog_cg internal exception - gq_ltmpspan - no defn
AVSREQ-173881 SIMVISION_MS AMSD mixed-signal activity stats reports different number of events compared to Mixed Net browser
AVSREQ-177721 DEBUG_DESIGN_DATABASE Xcelium cannot display isolation ports correctly
AVSREQ-181118 DMS_SOLUTIONS SV-UDN Profiler updates based on customer feedback
AVSREQ-174338 VHDL_CODEGEN xrun crash on VHDL: gq_e_selected - no tag
AVSREQ-176749 DEBUG_DESIGN_DATABASE Add environment variable to skip recording LP TextRefs
AVSREQ-178314 DEBUG_DESIGN_DATABASE Port of interface modport type in Hierarchy viewer in snapshot mode
AVSREQ-177037 DEBUG_DESIGN_DATABASE Missing "loads" when port are connected by OOMR
AVSREQ-178963 POWERPLAYBACK_GENERAL tool error when adding comment to Delayfile
AVSREQ-168003 RAND_SOLVER Assertion failure in librnc
AVSREQ-183572 DMS_QUALITY Elaboration exits with vsto_class() - mixed bus, class 520
AVSREQ-171260 SIMVISION_DB_UTIL simvisdbutil issues segmentation fault message converting SHM to CSV
AVSREQ-160770 LP_DOC callback objects are not updated when declared in UVM env.
AVSREQ-183446 LP_INFO_MODEL_AND_QUERY UPF_GENERIC_PRE_ISO missing full hierarchical path
AVSREQ-180801 FUNC_SAFETY_CONCURRENT Concurrent Engine Crash
AVSREQ-179567 SV_DPI Internal error using DPI SV code
AVSREQ-181559 DEBUG_DESIGN_DATABASE Indago stops responding while starting up for more than 10 mins
AVSREQ-176545 MSIE_SIMULATION MSIE interface optimization causes crash
AVSREQ-179364 SV_PARAMETERS Elab Internal error
AVSREQ-176380 SIM_SV_VHDL Issue with dynamic array of struct from SV to vhdl
AVSREQ-186124 PARSE_SV xmvlog stops in customer's case with latest Agile (works fine with 22.12-A)
AVSREQ-179889 LP_1801 Xcelium report CSNMCN error message
AVSREQ-184691 DEBUG_PROBE Simvision/Indago tools exit unexpectedly when run with glitch_detect
AVSREQ-183641 LP_SIM_PERF Incorrect sim behavior, value change without clock edge
AVSREQ-170353 DEBUG_DESIGN_DATABASE Indago does not show input interface when module instantiated inside if statement
AVSREQ-172762 SIM_EVCD Evcd dump using tran primitive
AVSREQ-179806 DMS_LP_AMS LP_MS: MPSSCN error on add_power_state attributes defined in hard macro power model in customer test-case
AVSREQ-129410 ASSERTION_SVA function not getting called again in an assertion
AVSREQ-185529 VWDB_XCELIUM Native FSDB dumper not working in Agile7 release
AVSREQ-182139 PROFILER_SIM_RUNTIME Merged profile report numbers are wrong
AVSREQ-179529 DMS_AXUM xmsim: *E,ILLNUM: Expecting an integer or real numeric literal (tstops).
AVSREQ-173680 SIM_PERFORMANCE 4x build memory degradation with VTW local array options "-ENABLE_VTW_LOCAL_ARRAY"
AVSREQ-181044 DMS_LP_AMS AMS co-sim. crashes with internal exception in LP+MS - pwr_merge_nets
AVSREQ-180336 LP_1801 incorrect behavior for expression evaluation while domain is off when RHS includes all always_on signals
AVSREQ-165791 VPI_GENERAL SimVision Design Browser crash upon expanding hierarchy
AVSREQ-174127 FUNC_SAFETY Inconsistent DHE db: hierarchical instances declare leafs that are not in the same db
AVSREQ-178716 LP_1801 xlm builds with LowPower hung with either -createdebugdb or -lwdgen
AVSREQ-156464 LP_1801 Enhancement for not corrupting constant connected to a port
AVSREQ-180397 POWERPLAYBACK_GENERAL Powerplayback - PIs are not initialized if they have delays in delay file
AVSREQ-178583 SIM_PERFORMANCE Different simulation behaviour with and without -linedebug
AVSREQ-177165 POWERPLAYBACK_GENERAL change PPB debug output file and mapping rate format
AVSREQ-104105 IP_PROTECT_GENERAL Need to display RTL ports in encrypted code
AVSREQ-164911 SIMVISION_GENERAL Order by time enhancement needed in open simulation form
AVSREQ-174938 SV_PORTS xmelab: *E,PCIONC: Expression connected to an 'inout' port must be collapsible.
AVSREQ-178950 XRUN_GENERAL xrun: *E,MKDIRP: Unable to create the subdirectory (xllibs)
AVSREQ-179699 SIM_SV *F,INTERR: INTERNAL EXCEPTION
AVSREQ-186771 VPI_GENERAL xmelab: *F,INTERR: INTERNAL EXCEPTION with MESSAGE: Bad argfile read -incdir
AVSREQ-180926 DEBUG_PROBE Enhancement for $shm_open / -function / ida_probe / -event / -wave_glitch_recording
AVSREQ-177285 SV_PORTS xmelab hangs when -enable_clk_fwd_opt is used
AVSREQ-185773 ELAB_CLONE xmelab stops in superunit design
AVSREQ-176988 ELAB_PERF Corrupted directory names in tools. lnx86/inca/files/
AVSREQ-181855 DMS_ELAB Show filename and line number for -dms_trace_coercion results
AVSREQ-173338 SIM_SV SIGUSR from rts_uvm_hdl_read
AVSREQ-185188 DMS_LP_AMS AOILPE message does not point to any file or module
AVSREQ-180640 SIM_SV Display an unwanted SIGNOC message for undefined initial value.
AVSREQ-179443 DEBUG_DESIGN_DATABASE "-xmclone" stops elaboration response
AVSREQ-176138 GLS_GENERAL Output of "and" primitive is unknown at 0ns
AVSREQ-181096 FUNC_SAFETY Why transient fault (SET) is not released after time?
AVSREQ-182894 GLS_TIMING xmelab: *F,INTERR: INTERNAL EXCEPTION, apx - can't abstract pointer, 0x06dbd8 of 0x15ed9868
AVSREQ-175446 IP_PROTECT_GENERAL xmprotect: *E,ENCERR: (test.vhd,0) Error during encryption. invalid or unknown or incomplete pragma specification '–pragma protect begin'.
AVSREQ-184785 RAND_SOLVER Inside constraint appears to be ignored
AVSREQ-178026 RAND_SOLVER xmsim: *F,RNDUNR: XCELIGEN assertion failed - solve_consistent_with_init
AVSREQ-180703 SIMVISION_TCL Simvision-inserting expression into group -not working if expresssion name and database/session name are same
AVSREQ-184746 GLS_GENERAL Issuing elab exit : MESSAGE: nettmp_fetch - id out of range
AVSREQ-185147 SIM_PERFORMANCE -enable_delbuf_with_write causes apx failure in xmclone
AVSREQ-179242 ELAB_PERF newperf options -enable_portbit_select_opt and -enable_oomassoc_opt are ineffective
AVSREQ-122257 LP_1801 lps_logfile generated log file is in append mode
AVSREQ-179307 DEBUG_DESIGN_DATABASE Missing driven_signals - with OOMR interface assign
AVSREQ-179804 POWERPLAYBACK_GENERAL G2G delay file mapping rate is 100% but G-exist rate is low ~0%
AVSREQ-178829 SV_DATATYPES Request to support passing events by references using ref keyword
AVSREQ-180491 DMS_ELAB xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-174586 SPECMAN_COMMANDS Frequent GCs after reload
AVSREQ-183913 PARSE_SV -enable_statement_macro_debug prints out verbose messages every time it encounters a macro
AVSREQ-183715 SIM_PERFORMANCE Performance switch bug
AVSREQ-179015 RAND_SOLVER parameter used in randomize constraint fails
AVSREQ-178849 ELAB_SV xmelab: *E,DLNORD: Intermediate file for verilog_package
AVSREQ-184490 SIM_VHDL write in files from vhdl processes are sent to smartlog whereas it is not the case with verilog
AVSREQ-164217 SV_PORTS Unsupported Interface slice in instance
AVSREQ-181977 VHDL_PERFORMANCE Xcelium BDOPT error with '-enable_vhdl_vect_opt_sens_sig'
AVSREQ-182926 LP_1801 Missing power model & hard macro instance
AVSREQ-175812 MCE_SIM_FAILURE MCE runtime crash
AVSREQ-180216 DEBUG_DESIGN_DATABASE lwd_complete flow should not need the elab/-lwd_prepare to be re-done in case the lwd_complete command failed
AVSREQ-173383 DOCUMENTATION Add always_trigger to Xcelium Command-Line Quick Reference
AVSREQ-182431 SIM_PERFORMANCE X's seen on the port despite when waveform dump is enabled. As per the input logic the signal should have been 0.
AVSREQ-180901 SIM_PERFORMANCE elab takes 1h 20m with extra 130k cover property
AVSREQ-174399 LP_ISOLATION Missing isolation when using set_repeater
AVSREQ-183524 RAND_SOLVER Different seeds generate same sequence
AVSREQ-179551 DMS_ELAB Add -dms_udn_profiler to enable the VPI based UDN profiler
AVSREQ-147234 COVERAGE_COVERGROUP xmvlog : *E, UPITEM - Covergroup declarations inside a compilation unit scope are not supported.
AVSREQ-172674 ELAB_PERF Build performance degradation on checkpoint cu_do_ots: topological_sort
AVSREQ-179583 SPECTRE_AMSD amsspice: hdl module bus port cannot be in expanded form when it is instantiated in a subckt (spice-in-middle)
AVSREQ-170584 XPROPAGATION_PERFORMANCE XPROP causes 7X slower elaboration time
AVSREQ-174587 ASSERTION_SVA E,SELPRV - Use of variable or variable-index in the select expression inside the sampled value function $past is not supported.
AVSREQ-185327 ELAB_SV Provide lib.cell:view information in TYCMPAT error (unpacked struct)
AVSREQ-171525 PARSE_SV Add feature to provide report of uvm_hdl_force & uvm_hdl_deposit calls during parsing
JIRA ID COMPONENT SUMMARY
AVSREQ-177786 JUPITER_BRIDGE elaboration crash with MultiCore
AVSREQ-178556 MSIE_ELAB xmelab: *E,DPMSIE : Default value parameter is not supported in MSIE
AVSREQ-167897 UVM uvm-ieee does miss essential perf fix in uvm_resource
AVSREQ-123117 LP_ISOLATION do not create NOCNINP if port is not driving anything
AVSREQ-184865 LP_1801 LPSNOSN Soft Error identifies the $supply_on / $supply_off in upf_package.sv
AVSREQ-181881 LP_1801 Add a warning to Xcelium when port attributes are ignored from invalid directions
AVSREQ-174497 MSIE_ELAB Enable -libverbose for MSIE genhref log under -enable_libverbose_genhref
AVSREQ-181869 POWERPLAYBACK_GENERAL PowerPlayback : extensions of liberty file list.
AVSREQ-180561 POWERPLAYBACK_GENERAL Power Playback generate tcl command with more space
AVSREQ-184736 COVERAGE_COVERGROUP *F,INTERR: INTERNAL EXCEPTION in xmvlog_cg(64) 22.12-a071
AVSREQ-186430 MSIE_ELAB Make -XMSIE_EXCLUDE_DEFPARAMS default and create a backward compatible disable option
AVSREQ-177138 LP_1801 <NonPA> module is recognized power aware model by *W,PWASSCI
AVSREQ-170693 SIM_PERFORMANCE 1.05x sim memory gap wrt competition
AVSREQ-168389 ELAB_CLONE xmclone msie internal error with href
AVSREQ-177745 SIM_PERFORMANCE Elaboration TAT of 22.04.a071 is 30X slower than 18.09.s017.
AVSREQ-176084 RAND_SOLVER Provide option to ignore all soft SB semantics and heuristics
AVSREQ-178826 LP_1801 Add latest UPF Linter to Xcelium
AVSREQ-176951 DEBUG_DESIGN_DATABASE Need a way to break on abnormal lwdgen exits
AVSREQ-162795 ASSERTION_VPI Assertion VPI callback issue
AVSREQ-186453 VST_PRIME xmelab crash with latest nightly agile (build w/ synth. rams) #1
AVSREQ-176145 SR_BACKDOOR TRAT_NOT_IMP crash when running with xmml generated backdoor file
AVSREQ-177305 SYSC_GENERAL Don't use COV01 to enable SystemC coverage
AVSREQ-179271 XPESSIMISM_GENERAL In merged corr file, hier macro and module name should not be encrypted
AVSREQ-162746 LP_COV_VERIFY We'd like to get Power_States_Tables on IMC with add_power_state
AVSREQ-175738 COVERAGE_COVERGROUP CG name as full_path is not showing in IMC
AVSREQ-176600 SV_CLASSES xmelab internal error with seg_handler message.
AVSREQ-161518 ELAB_PERF XRUN time is too high in comparison to xmvlog+xmelab in automsie flow
AVSREQ-177482 SPECTRE_AMSD Cleanly exit when user tries to run AMS with XDP
AVSREQ-181128 RAND_SOLVER Unexpected randomization result
AVSREQ-177717 SIM_PERFORMANCE Assertions failing only with -enable_cdp_oblit switch; w/o -newperf or with -disableopt switch tests are passing
AVSREQ-179807 SV_CODEGEN Code generation internal error in customer design
AVSREQ-178435 SV_CODEGEN Newperf switch is causing a UVM_FATAL error
AVSREQ-159763 COVERAGE_FUNCTIONAL Enhancement to set_optimize -withexpr
AVSREQ-176397 ELAB_BIND bind for interface error: xmelab: *E,CUVUNF
AVSREQ-178749 ASSERTION_SVA -ii_warn pointing at module instead of line of code
AVSREQ-175094 VPI_GENERAL Enhance xm_newinitialize to also include all registers, along with UDPs
AVSREQ-182743 SV_INTERFACE xmelab: *E,CUTMNI due to array of modports in interface.
AVSREQ-178622 DMS_ELAB Improve CMINHD messages with instances location
AVSREQ-167359 SIM_SPARSE_ARRAY xmsim run time memory is 10 times more
AVSREQ-179537 SPECTRE_AMSD Analog force and release from TCL with Spectre X and APS and classic
AVSREQ-179252 28447 VHDL ports are not shown in the Schematic
AVSREQ-180911 DMS_ELAB FATAL: Segmentation fault during elaboration phase
AVSREQ-179031 LP_LIBERTY Fail to pass environment variables into xmlib2cdb and on the command line without expanding it upfront
AVSREQ-184413 ELAB_SV Extra option-enable_bwcp_in_xmclone should not be needed to enable -enable_bind_with_common_pkg feature in xmclone
AVSREQ-179336 PROFILER_XPROF Adding -xprof in elaboration causing simulation failure
AVSREQ-179354 GLS_TIMING internal exception on elaboration with timings.
AVSREQ-175845 LP_TCL TCL: force -show does not explicitly display the source file path and its corresponding line number
AVSREQ-177633 SIM_SV stop -object fails on specific index
AVSREQ-180805 PARSE_SV parameter textref missing if RHS of parameter default is a -1 macro value
AVSREQ-168284 PARSE_SV XMVLOG parser not erroring when `define with newline has `endif in the subsequent line
AVSREQ-177669 PARSE_SV Compile crash without bpad error
AVSREQ-176690 SIM_SV xmsim crash with backtrace: rts_uvm_hdl_read
AVSREQ-178076 SIM_SV Value reverts to 0 in associative after 4 billion writes
AVSREQ-174653 SPECMAN_GENERAL OS signal 11 at 'Restart from Checkpoint'
AVSREQ-178683 FUNC_SAFETY_CONCURRENT rts_abrthandler - SIGABRT unexpected violation
AVSREQ-175577 GLS_PERFORMANCE Xcelium GLST simulation performance is slower than competitor
AVSREQ-178054 LP_1801 Value of key "upf_generic_source" of "query_isolation" command is 'null' if the signal is driven by module that is power aware with liberty
AVSREQ-178857 ELAB_PERF After bringing up Indago GUI, source pane is empty
AVSREQ-182438 SIM_SAIF_TCF Xcelium report warning message SAFNOBJ when dumping saif file
AVSREQ-183419 ESW_ESWDBGEN xmsim: *E,ESWDBWRERR: Error occurred when generating esw.db
AVSREQ-186423 LP_DOC please correct the descriptin of set_simstate_behavior
AVSREQ-184907 LP_1801 Elaboration failed with internal exception with UPF
AVSREQ-176581 LP_SIM_PERF performance enhancement for mss v2 UPF
AVSREQ-177345 COVERAGE_FUNCTIONAL How to deselect the covergroup coverage of selected hierarchy and its sub-hierarchy
AVSREQ-183036 UVM_REG get_reg_by_name causes segmentation fault
AVSREQ-146772 SIMVISION_MS Need equivalent TCL command for Browse Currents
AVSREQ-175968 SV_GENERAL Incorrect determination of array index width
AVSREQ-177197 SIMVISION_GENERAL It takes time till simvision is up. It looks for Indago_VB_SV Feature.
AVSREQ-181600 SV_PARAMETERS Met with a lot of VALFIT warnings (AI Team)
AVSREQ-183151 SIM_PERFORMANCE Competition's matrix multiplier tests failed
AVSREQ-177160 RAND_DEBUG *F,XGROPENWR exists as .xceligen.db is considered missing
AVSREQ-179060 SIMVISION_SIGNAL_TRACING Need a utility to filter currents and voltage above or below a certain threshold in SimVision measurement window
AVSREQ-176529 ELAB_CLONE xmelab crash observed when using -XMCLONE_MIN_PCT 0.01 (or 0.005)
AVSREQ-183867 SIM_SV Mismatch between x86 and aarch64 - struct being updated unexpectedly
AVSREQ-167722 LP_INFO_MODEL_AND_QUERY Add support for MODEL INFORMATION's elements_UPF_GENERIC_ASYNC_LOAD & elements_UPF_GENERIC_CLOCK
AVSREQ-180117 LP_1801 Xcelium report UPFERRM when upf command mix 2.0 and 3.1 version
AVSREQ-175893 LP_CPF xmelab giving *E,XPFMPAR: [LPS] Mismatched parentheses in control condition in 21.12.001
AVSREQ-177604 PARSE_SV Wrong source markers on errors coming from nested macros
AVSREQ-178369 ASSERTION_SVA UNDIDN Error for array reduction function sum using with clause
AVSREQ-181270 RAND_SOLVER constraint solver failed - message: solve_consistent_with_init
AVSREQ-123953 SYSC_GENERAL xmshell ignores ports from parent classes
AVSREQ-178513 MSIE_ELAB MSIE genhref gets degraded in build time with xform_lite options.
AVSREQ-180280 LP_ISOLATION dangling ack was not flagged multi-driver error/warning and should not have been allowed to isolate
AVSREQ-176764 SV_CODEGEN Internal Error: gq_cfjb - loop back corruption
AVSREQ-181029 DMS_ELAB -dms_relax_ro_wire does not ignore assign statement on undeclared wire in unused part of generate if-else construct
AVSREQ-182749 VST_PRIME With "-setenv XM_CA_INLINE_EXT_UNPROTECTED=1", the elab fails
AVSREQ-181709 DMS_LP_AMS The error MPSSCN is reported incorrect for power model set on spice skeleton
AVSREQ-176873 ELAB_PERF Add -enable_constfn_loop_eval_opt under newperf
AVSREQ-178000 GLS_GENERAL Driver command doesn't show exact drivers while debugging tran network
AVSREQ-183118 XRUN_GENERAL worklib_-3.ts getting touched when running simulation which causes recompile with no code change
AVSREQ-176580 LP_1801 VHDL checkers bound to the design are replayed despites lps_bind_aon
AVSREQ-173206 SV_PERFORMANCE Test in new project gets stuck at time 0 for 2 more mins than old one
AVSREQ-179633 DMS_AMSD $temperature reports number just a bit too high
AVSREQ-177865 SYSC_GENERAL Add support for –srcdir to resolve relative path issues.
AVSREQ-184695 PARSE_SV *W NOUNAD Unexpected
AVSREQ-176984 SIMVISION_GENERAL Opening vwdb with simvsion doesn't produce error notification.
AVSREQ-176587 SIM_PERFORMANCE INTERR with cu_PES_check_func due to prune
AVSREQ-174851 PARSE_SV *F,DLHVAR when running env -I <path_to_xlm>/tools/bin/xrun
AVSREQ-180556 DMS_ELAB crash during elaboration with message "vst_name() - invalid class, class 749"
AVSREQ-176527 GLS_TIMING Xcelium report Internal Exception in xmelab stage
AVSREQ-184523 SIM_SAIF_TCF Enhance output SAIF format for special words
AVSREQ-180383 LP_ISOLATION unclear ISOEQPC elab error when using -lps_iso_elem_precedence_on
AVSREQ-173004 IXCOM [xcBidir/xcDesignTop] xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-179221 LP_BUILD_PERF Enable ftg_sharing optimization with rnm_coexist mode
AVSREQ-182657 SIM_TCL Tcl command strobe cannot handle escaped instance names
AVSREQ-172560 SPECMAN_COV ignore coverage item option with HDL path fails
AVSREQ-177232 DEBUG_DESIGN_DATABASE Arithmetic operation on digital waves should produce a digital result
AVSREQ-177872 SIM_PERFORMANCE Customer's 15th July tree is crashing on nightly agile run
AVSREQ-175899 MSIE_ELAB AutoMSIE partitioner finetuning for customer design
AVSREQ-144960 SPECMAN_PERF Wrong values of Approximate relative GC time at load time
AVSREQ-183607 SPECMAN_COV vManager "Bin Filter" breaks coverage model
AVSREQ-180864 PARSE_SV xmvlog: *E,SPFWDUSpecialization of forward type declarations is currently unimplemented
AVSREQ-100791 DMS_VLOG VAMS parser: xmvlog should error out for invalid variable used in analog function
AVSREQ-183132 COVERAGE_GENERAL xmelab INTERR: vst_immediate_scope() - bad class, class 1023
AVSREQ-176435 SV_PERFORMANCE Performance enhance request #2 for Modem IP
AVSREQ-176339 PARSE_SV xmelab: *E,FEWCAA : Foreach illegal for wildcard index of associative array.
AVSREQ-167937 LP_1801 Phase-2: buf primitive as a feed-through wire using a config file
AVSREQ-174250 ELAB_SV RTL and GLS simulations seeing simulation crash
AVSREQ-169042 ELAB_PERF Elab : INTERNAL EXCEPTION
AVSREQ-187573 SIM_PERFORMANCE Xcelium Simtime Crash with 23.01 release with -ENABLE_CONST_FORCE_OPT
AVSREQ-179973 MSIE_PERFORMANCE Create an msieunlock simperf_fastbuild umbrella option and add options inside that
AVSREQ-179814 DEBUG_DESIGN_DATABASE "-automsie" stops elaboration response
AVSREQ-175627 ELAB_CLONE Design hierarchy summary module instances number gets WRONG when testcase is run with xmclone and leaftbe together
AVSREQ-180544 DEBUG_DESIGN_DATABASE Indago failed to trace drivers from Class
AVSREQ-168211 SIM_PERFORMANCE reset -sync and memopt are incompatible
AVSREQ-184179 SPECTRE_AMSD Is there a way to get rid of parentheses surrounding net name in bundled port
AVSREQ-181974 LP_1801 Phase 1B - create message for back-to-back isolation failure -no_iso
AVSREQ-176436 SIM_PERFORMANCE Performance enhance request #3 for Modem IP
AVSREQ-160495 ELAB_PERF Build performance issue due to enable_unique_viewname
AVSREQ-99982 SIMVISION_GENERAL Show e source code failure after simulator reinvoke
AVSREQ-182331 SPECMAN_E UVM-ML enhancement - using uvm_config_set in parallel hierarchy
AVSREQ-179018 SIM_SV xmsim:*F INTERR crash intermittently
AVSREQ-174024 RAND_DEBUG MESSAGE: sv_seghandler - trapno -1 addr((nil))
AVSREQ-182247 GLS_TIMING track option to ignore pathdelay input to same input
AVSREQ-178109 SV_PARAMETERS Crash during elaboration
AVSREQ-184831 SIM_PERFORMANCE different behavior on simulation with vs without dump
AVSREQ-180338 LP_INFO_MODEL_AND_QUERY Deprecate -lps_qry_exp_supp and introduce new umbrella switch -lps_im_advance_info
AVSREQ-167471 POWERPLAYBACK_GENERAL XMREPLAY_SIGNAL_REPLAY_FILE to support constant 1'b0/1'b1 replay
AVSREQ-182886 ELAB_CLONE xmelab crash: "MESSAGE: smm_protect() - unable to protect" (w/ -XMCLONE_MIN_PCT 0.025)
AVSREQ-176392 SIM_SV xmsim: *F,INTERR: INTERNAL EXCEPTION - cod_pctosm - pc not in sp
AVSREQ-180521 LP_LIBERTY Applying liberty files of 2 different technology nodes on a single verification environment for 3D-IC
AVSREQ-173885 LP_1801 Incorrect NOISELE error for isolation strategy with only cell element
AVSREQ-176511 PARSE_SV Assertion warning for boolean implication -> operator
AVSREQ-185531 LP_RETENTION Xcelium should not split sub-strategies based on clock sense for UPF_GENERIC_CLOCK
AVSREQ-186110 MSIE_ELAB Performance issue introduced by cu_msie_is_child_up()
AVSREQ-180658 ELAB_SV sv_seghandler - trapno -1 addr(0x12) with DPES optimization
AVSREQ-167082 ELAB_SV various xmelab crashes
AVSREQ-181987 LP_1801 access required for code created by bind_checker
AVSREQ-182432 SV_DATATYPES segfault during elab
AVSREQ-178641 SV_CLASSES uninformative TYCMPAT message. how to get more info
AVSREQ-184686 DMS_ELAB AMS elaboration stops with F,INTERR
AVSREQ-177060 PARSE_SV Support of wildcard operator representing multiple v/sv files in libmap
AVSREQ-186362 VWDB_XCELIUM Native FSDB conversion doesn't happen when xrun has the -nolog switch
AVSREQ-184189 SIM_VHDL 10% simulation performance degradation when moving from 21.09 to 22.12
AVSREQ-176385 MSIE_SIMULATION Simulation hanging with MSIE cold/warm flow
AVSREQ-171645 SPECTRE_AMSD SimulinkCoupler:Block Parameters Number of Pins Limit 0~100 But Circuit Over 100 Pins
AVSREQ-160278 ELAB_SV sv_seghandler - trapno -1 addr(0x7ffecd1a5ff8) during elaboration.
AVSREQ-178589 IP_PROTECT_GENERAL LEVEL1AUTOPROTECT for VHDL
AVSREQ-182460 XRUN_GENERAL need xrun to ignore -cleanlib like -clean when it is used along with the -r or -R option
AVSREQ-178069 ELAB_CLONE Internal error in elaboration with tran gates, xmclone and DSS.
AVSREQ-159341 IXCOM uvm_hdl_read support for checkhwaccess/genhwaccess
AVSREQ-178968 ELAB_SV_VHDL Xcelium bb_list option could not blackbox with module name and could not work with bbconnect option
AVSREQ-157490 LP_INFO_MODEL_AND_QUERY Support for UPF_SAVE_SIGNAL, UPF_RESTORE_SIGNAL, UPF_CONTROL_SIGNAL
AVSREQ-168925 SV_RUNTIME $fread behavior for dynamic packed array : ($fread is not loading to highest address of memory as per LRM 21.3.4.4)
AVSREQ-173947 DMS_ELAB RL_Bidir converts real to Z when replication operator is used
AVSREQ-175362 SIM_PERFORMANCE Internal exception following version update from 20.03.001 to 22.03.004
AVSREQ-178287 SIM_SV -ii_warn messages writing out at the end of the sim when using TCL catch
AVSREQ-178947 GLS_PERFORMANCE clean up gate_oblit_driver performance
AVSREQ-153806 MSIE_ELAB *E,INCODP A defparam cannot set the value of a target parameter in another partition
AVSREQ-186756 XPROPAGATION_GENERAL Single-step MSIE simulation crash with XPROP and -msieunlock intf_optm_phase1/2
AVSREQ-153376 GLS_SDF -sdfstats option shows timing check removed using tfile as unannotated
AVSREQ-174539 SV_CLASSES *E,CLSNAA on uvm messaging macros with class nesting/param. inheritance
AVSREQ-181031 PARSE_SV Unexpected NOUNAD warning with Xcelium releases after 22.08 AGILE
AVSREQ-167763 SIM_PERFORMANCE MSIE: *W,VTWPPSNT: sanity check failure for conversion attempt, with -enable_var_opt_core
AVSREQ-183140 XRUN_GENERAL Incremental Build not working with autofetch
AVSREQ-179414 SV_INTERFACE INTERR with cu_PES_check_func due to prune
AVSREQ-180118 LP_1801 Xcelium report UPFERRM for add_port_state command
AVSREQ-183592 RAND_SOLVER Latest librnc crashes simulation
AVSREQ-100822 FUNC_SAFETY_CONCURRENT Concurrent engine encountered unsupported always block
AVSREQ-164832 LP_COV_VERIFY Dump power state table w.r.t. add_power_state command
AVSREQ-178724 SV_PARAMETERS xmelab hangs
AVSREQ-171113 SIM_TCL Tcl cmd issue: value check not working for unpacked array
AVSREQ-180053 VST_PRIME xform_lite crash on nightly agile
AVSREQ-179056 SV_PORTS xmelab gets stuck in deadcode optimisation
AVSREQ-176953 SIM_PERFORMANCE xmsim: *F,INTERR during 22.07.a071 Qual
AVSREQ-182014 ASSERTION_SIM Warning for assertions with high run time contribution
AVSREQ-180865 UVM_SV svSetScope returns null in DPI-C context function call
AVSREQ-178519 ASSERTION_DEBUG Warn memory hogs for assertions without -profile
AVSREQ-180109 ELAB_CLONE Xmclone crash
AVSREQ-183934 SIM_SV Mismatch between x86 and aarch64 - unexpected uvm_error
AVSREQ-181982 SIMVISION_MS Flow probe is not added to waveform window
AVSREQ-177863 ELAB_CLONE Occasional xmelab INTERNAL Exception with -xmclone
AVSREQ-103565 SPECMAN_PERF Option to configure memory to emit a warning when GC percentage exceeds a predefined value
AVSREQ-179663 XRUN_GENERAL xrun using read-only xcelium.d fails if xcelium.d is read only when using -collect_exe xmsim
AVSREQ-173354 POWERPLAYBACK_GENERAL Adjust Presim time from 0 to fix power switch chain cause X value
AVSREQ-182244 DMS_LP_AMS xmelab internal error when adapting a lp design to lpms
AVSREQ-181953 DMS_ELAB Get the name of resolution function from where a systask is called
AVSREQ-179653 PROFILER_XPROF 10000 line limit in xprof text report
AVSREQ-186009 LP_1801 GLS UPF flatten hierarchy ILLPRT errors for escaped names
AVSREQ-173805 DMS_ANALOG_ELAB analog_node_alias function aliases all bus bits as electrical for a mixed discipline bus
AVSREQ-180261 PARSE_SV xmvlog: *F,INTERR: INTERNAL EXCEPTION with Xcelium 22.09.001 with MESSAGE: Unexpected signal #11, program terminated (null)
AVSREQ-178693 ELAB_BIND Bind Enhancement for supporting multi-dimensional array of instances (interfaces & modules)
AVSREQ-91969 ASSERTION_SVA intersect fails when sequences admit only empty match
AVSREQ-182141 ASSERTION_SIM Assertoff performance of consolidated tcl command
AVSREQ-176993 SIM_PERFORMANCE xmelab crash with "gate-clean-net next set"
AVSREQ-177229 LP_BUILD_PERF Checkpoint LP - after UPF Parsing is very slow in customer testcase
AVSREQ-171937 LP_LIBERTY xmlib2cdb should not report TECHLIB codes listed
AVSREQ-167501 LP_1801 Boundary port corruption is not being performed on primary output of a hard macro
AVSREQ-171570 ASSERTION_SVF [Xcelium]Using "$past" in a "$display" statement [xmvlog:*F,INTERR]
AVSREQ-177625 SIM_PERFORMANCE Elaboration is crashing with "super_prune" option
AVSREQ-180257 ASSERTION_SIM Behaviour of assertion with Xcelium
AVSREQ-147755 ASSERTION_SVA Simulation failure due to Assertion behavior mismatch between XLM and competition
AVSREQ-173681 SIM_PERFORMANCE 15% build time degradation with newperf
AVSREQ-180002 ELAB_SV Incorrect hook up of function generated index during elab
AVSREQ-185342 PARSE_SV "if_mapline - logical line not found" xmvlog stops for customer
AVSREQ-180515 ELAB_CLONE xmsim crash with "ifmgr - pt_build() - size calculated incorrectly" message with xmclone_memopt
AVSREQ-170106 LP_INFO_MODEL_AND_QUERY xmelab: *E,URCEN (XX_seq_item.svh,136|24): Unresolved constant expression VST_T_IMPLICIT_LOOP_VARIABLE_DATATYPE_OF
AVSREQ-183818 ELAB_CLONE Internal error with -mkprimsnap and xmclone
AVSREQ-177973 DEBUG_DESIGN_DATABASE Fatal during elaboration
AVSREQ-181508 SPECTRE_AMSD Regarding cds_internal_stub node signal introduced by simulator
AVSREQ-176931 SIM_RACEDT Wrong Race (RACERAW) reported
AVSREQ-181813 PARSE_SV Missing Error when Calling an SV function without passing parameters in class (works in module)
AVSREQ-183945 MSIE_ELAB Indago won't load LWD when one of parallel elaboration was used only on an unused primary
AVSREQ-180559 DEBUG_DESIGN_DATABASE Indago missing Loads (OOMR in function)
AVSREQ-163393 DMS_ELAB xmelab: *E,CUNMOA (./top_ana.sv,26|36): SystemVerilog interface modport signal connected to a VAMS signal is not supported
AVSREQ-124559 ELAB_PERF nested generate for loops impacting - xmelab performance issue
AVSREQ-95466 COVERAGE_TOGGLE Toggle Coverage icon missing from Source Code for an input containing a packed struct
AVSREQ-179712 VPI_PLI VPI error – Unexpected VST of type 738 in internal PLI routine ipi_findHandleInExpression.
AVSREQ-161971 SV_PORTS Expecting a warning while an implicit net is connecting to 2 ports which are defined as outputs
AVSREQ-178752 DEBUG_DESIGN_DATABASE Verisium Debug stops responding while opening LWD
AVSREQ-184786 MSIE_ELAB Provide a soft error on starting of MSIE Simulation when any of the elaborated primary snapshots is run with wildcard href
AVSREQ-182261 POWERPLAYBACK_GENERAL Power Playback miss toggle the signal when the toggle is at end of replay time
AVSREQ-174350 SPECTRE_AMSD Current Browser shows incorrect current when probing the current on a bus bit net
AVSREQ-182763 ELAB_CLONE Using latest RC kit (w/ -xmclone) shows build taking more time and memory
AVSREQ-177038 ASSERTION_SIM xmsim: *W,ABVMTO: More than one -ABVOFF option found, only the first option will be considered.
AVSREQ-171697 SPECMAN_COMPILE generated C code compilation fails
AVSREQ-133011 LP_1801 lps_logfile is always appended and not overwritten
AVSREQ-167984 DEBUG_DESIGN_DATABASE 'range operator not supported by simvision when accessing a scope
AVSREQ-175830 SPECTRE_AMSD EEnet_to_e_Bidir connect module assumes 1ns timescale
AVSREQ-183749 DMS_LP_AMS Elaboration exits without proper message with UPF
AVSREQ-185807 PARSE_SV xmvlog stops with "mapline - logical line not found"
AVSREQ-102421 DMS_ELAB Example of using $SIE_input not behaving as expected
AVSREQ-179093 LP_1801 SPA -literal_supply should win precedence over SPA -driver_supply
AVSREQ-180351 SIM_PERFORMANCE xmelab perf degradation from 21.03.v2 to 22.03.v2
AVSREQ-170292 SIM_PERFORMANCE Long simulation time due to for loop in always statement
AVSREQ-168740 LP_1801 flag an error if port attributes are missing for a terminal boundary
AVSREQ-180696 LP_1801 CSN not working on escaped names with wildcard not printing ILLPRT errors.
AVSREQ-183268 SIMVISION_CONSOLE Simvision scope command error with hierarchical path having a special character
AVSREQ-184941 SV_LET Failure during elaboration
AVSREQ-180631 LP_1801 CAC -lib_model change for disabling and enabling assertions
AVSREQ-162899 XPROPAGATION_GENERAL XPDIS when multiply driver not the same array cell
AVSREQ-177066 SIM_PERFORMANCE xmelab crash with -MSIE_STITCH_OPT_LEVEL 2
AVSREQ-89115 DEBUG_DESIGN_DATABASE Simvision plots `wrealXState and `wrealZState in EEnet as NaN
AVSREQ-182944 SIM_PERFORMANCE xmelab *F, INTERR
AVSREQ-182841 GLS_SDF Unexpected UDP behaviour
AVSREQ-180375 SV_CLASSES xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-167525 SIM_SPARSE_ARRAY Long test takes run time xmsim 10 times more memory than competition (now 1.4GB vs .7 GB)
AVSREQ-185640 RAND_SOLVER Unexpected randomization result
AVSREQ-177440 ELAB_BIND Need alternative for -top which is not controlled by config/any libmap rule
AVSREQ-156865 LP_ISOLATION Support set_level_shifter -input_supply_net / -output_supply_net
AVSREQ-182433 VPI_GENERAL Need a single click on class handle to jump to Class definition on source browser
AVSREQ-168144 LP_DOC set_simstate_behavior syntax has an extra dash before DISABLE
AVSREQ-175500 ASSERTION_SVF xmvlog: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-170678 LP_1801 Assertion triggered when there is no negedge of the signal
AVSREQ-182145 DEBUG_DESIGN_DATABASE Indago failed to open LWD when adding xrun option "-automsie"
AVSREQ-180701 SIMVISION_GENERAL Zoom to full on x and y axis when a simulation is finished in SimVision
AVSREQ-180139 POWERPLAYBACK_GENERAL Power Playback support 3rd party mapping file for POWERPLAYBACK_EXTRA_NAME_MAPPING_FORMAT
AVSREQ-181837 ELAB_VHDL TRINTOVF: integer overflow error not specific
AVSREQ-162799 SYSC_RUN Duplicate C files cause xrun to fail
AVSREQ-172992 VHDL_PARSE Compilation error *E,UNSPPU because of unsupported Constructs of VHDL 2008
AVSREQ-181733 MSIE_ELAB UVM Error in multi-xrun MSIE : PIX ACA table : snapshot name limitation : error check
AVSREQ-179026 SV_GENERAL Simulation divergence from UVM library due to UVM_VERBOSITY
AVSREQ-175873 SIMVISION_CONSOLE [Xcelium][SimVision] "invalid command name "0" error on "SimVision>scope show top.\X[0]".
AVSREQ-182633 DEBUG_DESIGN_DATABASE Watch window not showing values of queue elements
AVSREQ-130419 SIM_PERFORMANCE Verilog task calculation at time=0 is so heavy
AVSREQ-181144 ASSERTION_PERFORMANCE assertion tcl multi line with one line with RPTNAG warning
AVSREQ-173792 ASSERTION_SVA fail to compile a complex local var property
AVSREQ-167140 SIM_FORCE_RELEASE Xcelium GLST simulation performance (TCL forces on scalars with repeat) is more than 2x slower than competitor
AVSREQ-182513 LP_1801 UPF Parsing perf issue with SPA -is_analog
AVSREQ-173044 ELAB_SV *E,EXCKILL during elaboration
AVSREQ-179727 SV_PARAMETERS xmelab error NDPIFP in nightly agile on customer design
AVSREQ-179415 SV_INTERFACE INTERR with cu_PES_check_func due to prune
AVSREQ-175967 SR_XEML Problem with relocated UCM and UCD files
AVSREQ-187145 UVM_ML_OA_FRAMEWORK wrong translation in vhpi2val in umm
AVSREQ-173323 SV_CODEGEN Crash at code generation with 22.03.a001
AVSREQ-174685 DEBUG_DESIGN_DATABASE VHDL array display no value on waveform when -lwdgen option added (works with indago -nolwd)
AVSREQ-181859 DEBUG_DESIGN_DATABASE [Xcelium][22.09-s002]INTERNAL EXCEPTION when using -lwdgen
AVSREQ-176950 PARSE_SV xmvlog *E,QAANBA on commented line
AVSREQ-177287 SV_CODEGEN Unexpected : xmsim: *W,SYSFMW with 22.03-s03 $sformat
AVSREQ-180504 PARSE_SV xmvlog *F,INTERR: vst_elem_datatype () - invalid class
AVSREQ-178014 ASSERTION_SVF xmvlog crash - ebs_samp_svf_in_cover: Sampled samp
AVSREQ-184231 ELAB_CLONE mkprimsnap xmclone crash
AVSREQ-179949 COVERAGE_CODE set_refinement_resilience results not resilient against Xcelium version update
AVSREQ-103574 SPECMAN_COMPILE Display load time and memory consumption for each loaded / translated file
AVSREQ-161501 SIMVISION_MS Add a way to display only analog or only digital signal object in design browser
AVSREQ-85771 COVERAGE_TOGGLE toggle cover icon not shown in IMC source
AVSREQ-181335 POWERPLAYBACK_GENERAL Power Playback out *E with the duplicated QN pin in R2G case - use both 3rd mapfile + extra_mapfile
AVSREQ-163413 LP_1801 find_object cannot find related instance and port
AVSREQ-175210 SV_GENERAL function cannot call external task
AVSREQ-175809 LP_1801 One of the initial blocks is not replayed on power up.
AVSREQ-185126 COVERAGE_FUNCTIONAL coverage transition bins results in fatal internal error
AVSREQ-177047 MSIE_ELAB xmsim: *F, INTERR: INTERNAL EXCEPTION
AVSREQ-181129 SIM_PERFORMANCE xmelab crash when coverage is enabled in customer design
AVSREQ-175027 COVERAGE_FUNCTIONAL CGIMNS and QAANBI for Multi Dimensional Arrays of covergroup instances (inside the class)
AVSREQ-181436 MSIE_ELAB Dump HAB incremental verilog config file template in genmsiedata
AVSREQ-180449 UVM_SV uvm_hdl_read reading MSBs incorrectly as "x"
AVSREQ-182679 MSIE_PERFORMANCE Multi-step MSIE has 40% simulation time overhead over monolithic
AVSREQ-177502 LP_ISOLATION Reformat -lps_iso_verbose/-lps_iso_bit_verbose output to be more readable by end user.
AVSREQ-178938 VHDL_PARSE RANGE_BOUND fatal error on boolean expression
AVSREQ-115442 XRUN_GENERAL customer model: xrun -f elab.f hangs for long period of time
AVSREQ-174950 ASSERTION_SIM Getting DLRESO error to restart and ELREZT error to reset
AVSREQ-184703 GLS_SDF -iocondsort causes xmelab: *W,SDFBVA: Compiled SDF file "mux_inst1.sdf.X" is version 1104, can only annotate with versions between 1104 and 1104 inclusive
AVSREQ-178313 GLS_GENERAL trireg didn't keep value
AVSREQ-177468 JUPITER_COMPILER *F,MCEASRT: mcebuild internal error
AVSREQ-174380 DMS_WREAL wrong wreal resolution with dms_new_dig_island
AVSREQ-174375 PARSE_SV Crash when calling "push_back" in ansi style
AVSREQ-189464 SIM_PERFORMANCE Simulations failing due to enable_ff_split and -enable_super_prune colliding with each other
AVSREQ-174359 SIM_SV XMSIM crashes with MESSAGE: T(0): sv_seghandler - trapno -1 addr((nil)) Parallel block sub-process
AVSREQ-186468 SPECMAN_INDAGO xmsim crashes after issuing simulator reset - Specman interactive
AVSREQ-168024 RAND_GENERAL Problem with -xceligen urandom_for_random leading to problems getting a valid pstate & VIA
AVSREQ-180567 VPI_LWD Indago Missing connection from the parent scope
AVSREQ-183587 FUNC_SAFETY_CONCURRENT MESSAGE: rts_abrthandler - SIGABRT unexpected violation pc=0x2b0627853387 addr=0x12bf5740001541d
AVSREQ-175395 LP_COV_VERIFY Disable default states from dumping in automatic state transitions also
AVSREQ-184938 SV_GENERAL TYCMPAT Error: Expecting datatype compatible with 'chandle' but found 'null' instead
AVSREQ-141103 VHDL_GENERAL xmvhdl_p: *E,UNSPUP: Unconstrained record subtype in Subprogram parameter of Record/Array of Records types is not supported.
AVSREQ-180395 SIM_PERFORMANCE elab take 6h - CP 'after cu_optimize::cu_zoptimize'
AVSREQ-162986 SIM_PERFORMANCE Memory leakage issue when using Xcelium 21.03 or 21.09
AVSREQ-177428 LP_1801 Allow both "-model" and "-elements" on set_design_attribute
AVSREQ-96778 SIMVISION_WAVEFORMS force is only possible from analog/ linear, not analog/ sample-hold
AVSREQ-170959 SV_DATATYPES TRNULLID : Associative array with 'x/'z index - unexpected behavior
AVSREQ-184431 LP_1801 xmelab: *F,ILLCPRT: [LPS] Illegal power switch control port reference ("!SLEEPIN1) encountered
AVSREQ-181746 DEBUG_DESIGN_DATABASE Indago loads unreadable source file (.gz file) when -debug_opts indago_pp is used
AVSREQ-178461 SV_CODEGEN Elab Crash: xmvlog_cg crash "gc_mov - class mismatch"
AVSREQ-177515 ELAB_BIND Create elab option that can dump the hierarchy with binding information in lib.cell.view format
AVSREQ-182313 MSIE_ELAB Single-step MSIE elab crash with -msieunlock intf_optm_phase1/2
AVSREQ-183531 UVM_INSTALL cdns_uvm_pkg additions need to be guarded with macros
AVSREQ-180591 POWERPLAYBACK_GENERAL Power Playback dump fsdb for subscope tcl cmd issue
AVSREQ-181226 POWERPLAYBACK_GENERAL Power Playback enhance replay presim value which get the input waveform
AVSREQ-175624 MSIE_ELAB reducing -xmclone_min_pct has partitioner performance impact
AVSREQ-87632 DEPRECATE_ELAB_GENERAL Remove *W,DSEMEL
AVSREQ-184629 PARSE_SV Unexpected behavior with lib.map and options : -enable_single_yvlib, -enable_libmap_with_yv
AVSREQ-176513 SPECTRE_AMSD top level node connecting to lower hierarchy via inherited connection is not saved in spectre.ic and spectre.fc
AVSREQ-166163 SPECMAN_OTHER_LANGUAGES C FLI add nested structs copy by value
AVSREQ-171819 SIM_VHDL TRINDXC error
AVSREQ-174921 LP_VHDL unwanted activation of VHDL process by a signal when power domain is switched OFF->ON but the signal does not change it's value
AVSREQ-180630 IP_PROTECT_GENERAL AUTOPROTECT adding unwanted ' \ ' when encrypting macro in included file
AVSREQ-182771 SV_CLASSES Fix gives failures for some TB still, follow-on from AVSREQ-178641 fix
AVSREQ-179424 GLS_PERFORMANCE huge elaboration overhead when moving from ZD to SDF simulations
AVSREQ-178731 DEBUG_DESIGN_DATABASE Verisium Debug is missing isolation notation
AVSREQ-171789 LP_1801 enhance add_renaming_rule to support upf objects
AVSREQ-181225 SV_DATATYPES Elaboration crash
AVSREQ-173105 LP_ISOLATION Support Level shifter on port, to enable corruption on output in below case
AVSREQ-180057 GLS_GENERAL Function of "Multi_driven" report at gate level simulation with tran. (Cont)
AVSREQ-180973 LP_1801 Phase 1A - create message for back-to-back isolation failure
AVSREQ-184097 VPI_LWD Customer's python api - can't read port information
AVSREQ-179460 SV_CODEGEN xmvlog_cg crash with via_xmay_modify
AVSREQ-168450 RAND_DOC Please document Xceligen's max_rand_calls option
AVSREQ-176965 POWERPLAYBACK_GENERAL report mapping rate on R paths get confused
AVSREQ-176389 ELAB_CLONE Build with xmclone is functionally failing during simulation. Monolithic sim works fine.
AVSREQ-159361 SV_DEBUG Simulation divergence when changing UVM verbosity
AVSREQ-182588 PARSE_SV xmelab *F error : apx - can't abstract pointer
AVSREQ-185256 IXCOM Using -target with xrun -hw flow causes xmsim: *E,DLOALB runtime error when VHDL is involved
AVSREQ-179638 RAND_SOLVER distreport reports passing variables as failure
AVSREQ-178824 GLS_PERFORMANCE See if the design with cell making heavy use of mulitple mux and udp flop
AVSREQ-173938 SYSC_COMPILER Makefile failure when the same file is included twice
AVSREQ-178431 SIM_PERFORMANCE xmelab exit gq_continuous_assign
AVSREQ-187086 SIM_PERFORMANCE Optimization for combinatorial always blocks inside generate…endgenerate
AVSREQ-178195 FUNC_SAFETY_ELAB Extremely long elaboration build time
AVSREQ-176655 LP_1801 upf_always_on HDL attribute doesn't work for top level ports with SPA
AVSREQ-176120 SPECMAN_INTEF session.timers_real list growing continuously causing memory explosion
AVSREQ-142035 SV_DATATYPES Event as ref arg to an automatic task is not working as expected
AVSREQ-186089 MSIE_ELAB Change MSCUOP to be a soft error and generate a partition file
AVSREQ-177307 SYSC_GENERAL Don't use covselect to enable SystemC coverage
AVSREQ-184934 LP_1801 xmelab: *SE,ILOBJUE: [LPS] No IEEE 1801/design object is found - create_logic_port/create_logic_net
AVSREQ-177096 GLS_GENERAL Is the -enctran option enabled by default in 22.06.a071?
AVSREQ-175396 LP_COV_VERIFY Port size difference from tool generated *_cov.sv file is causing issues.
AVSREQ-182585 SIM_PERFORMANCE Fix for logic wire conversion failure
AVSREQ-179003 SIM_PERFORMANCE More testbench builds crashing with '-enable_queue_prune'
AVSREQ-178805 GLS_SDF xmelab: *W,SDFNEP: Unable to annotate to non-existent path
AVSREQ-177222 COVERAGE_COVERGROUP COVUICGW notes given for CG that are in fact instantiated
AVSREQ-172829 LP_ISOLATION -lps_iso_hybrid should check isolation cell's enable signal and SupplySet against the rule
AVSREQ-175828 LP_SIM_PERF "Power On Reset" Functionality Issue
AVSREQ-177605 PARSE_SV Customer's 15th july tree compilation hang
AVSREQ-171624 SIM_PERFORMANCE Seeing 1.13x sim mem gap wrt competition for SCF
AVSREQ-179971 MSIE_SIMULATION MSIE fast build without simperf crashes on simulation with task parameter update message
AVSREQ-182552 UVM_ML DPI errors in UVM-ML test when Specman error occurs at Xcelium exit
AVSREQ-177859 SIM_PERFORMANCE Testbench build is crashing due to "queue_prune"
AVSREQ-176839 PROBE Waveform can't show value of dynamic array
AVSREQ-184721 LP_SIM_PERF FF output "q" changes the same time as input "d" changes
AVSREQ-172979 SV_PARAMETERS SVARPX: Unsupported element datatype for array parameter : -enable_multidim_strparam_uparr
AVSREQ-176122 LP_ISOLATION Extra ISO drops when repeater proc is used
AVSREQ-103582 SPECMAN_GUI events continue to be traced after 'trace event -wave -off'
AVSREQ-178413 SIM_PERFORMANCE -enable_multi_driver_prune or -enable_nba_opt causes unexpected value on a signal
AVSREQ-178951 SV_CLASSES INTERNAL EXCEPTION with MESSAGE: vsto_op_data - PARAMETER - no value, class 745
AVSREQ-177055 SPECTRE_AMSD analog publishing issue with Spectre terminals when running AXUM flow
AVSREQ-178743 PARSE_SV $bits computes parameter incorrectly
AVSREQ-180540 DMS_LP_AMS ams_get_bie_shadow_net internal errror
AVSREQ-181856 DMS_ELAB Add max number to limit detailed dms_trace_coercion report - performance consideration
AVSREQ-177799 SIM_CONGRUENCY Seeing incorrect assignment on output when input and condition signal are changing at the same time
AVSREQ-177763 LP_SIM_PERF Internal exception (xmsim) in LPS
AVSREQ-146311 LP_1801 SDA attribute UPF_dont_touch does not work for elements
AVSREQ-152105 SV_DATATYPES SVNIMP error on initialization of a int struct member
AVSREQ-171957 LP_COV_VERIFY Customer: Support PSW coverage for low power simulation by -lps_cov option
AVSREQ-175138 ELAB_CLONE Internal error : MESSAGE: sslu_descend - NULL sxp
AVSREQ-173030 SPECMAN_COV Memory corruption using cross item with complex ignore expression
AVSREQ-170760 RAND_SOLVER Two threads using $urandom are assigning the same values
AVSREQ-99727 PARSE_SV -incdir option usage inside the library map file
AVSREQ-170006 ELAB_SV INTERR with optimizations disabled
AVSREQ-181745 DEBUG_DESIGN_DATABASE Source browser can't see content of compiled zip code
AVSREQ-183425 MSIE_ELAB Autoref.txt contains <TAB> characters. Customer request to remove them
AVSREQ-95455 ASSERTION_SVA ncsim: *E,ABVNDG: Degenerate sequence used in assertion
AVSREQ-179514 DYNAMIC_TEST_SIMULATION $readmemh abnormal loading data issue in Dynamic Test case
AVSREQ-133303 SPECMAN_COMPILE How to get load time of each loaded / translated file
AVSREQ-174788 MSIE_ELAB Inefficient partitions resulted with automsie
AVSREQ-175966 SPECMAN_GENERAL Error : No notifications match : WARN_VERILOG_WIRE_UNDEFINED
AVSREQ-141358 PARSE_SV xmvlog: *E,WAAIND Indicated Index locator methods called on associative arrays with wild card index is not supported.
AVSREQ-176117 SPECTRE_AMSD parameterize vsup of ie card with AXUM use-model
AVSREQ-172169 GLS_SDF INTERCONNECT delay is ignored
AVSREQ-173127 LP_LIBERTY Fixing CUVPOM error during port connection, when instantiated module does not have power ports in HDL, but have them in liberty as pg_pins
AVSREQ-184890 SIM_PERFORMANCE -enable_delbuf_with_write option causes xmelab internal error cu_short_rhs_lhs
AVSREQ-177686 MSIE_SIMULATION MSIE Sim failure with partition soc_tb and soc at user testcase time 1472466587PS + 36
AVSREQ-167363 SIM_PERFORMANCE Simulations with -linedebug are very slow.
AVSREQ-178848 ASSERTION_DOC Please document -abv_disable_eos_eval
AVSREQ-171102 IXCOM CLONE - Please provide xmsim.o compiled w/ -fPIC ixcom_dpi_hook cases
AVSREQ-179165 SIM_PERFORMANCE xmelab : *F, INTERR, INTERNAL EXCEPTION
AVSREQ-177048 GLS_PERFORMANCE Encountered "INTERNAL EXCEPTION Error", when added "-LPS_1801"option
AVSREQ-183747 PROFILER_SIM_RUNTIME GCPU: Indendation misalignment with "Miscellaneous"
AVSREQ-181339 DEBUG_DESIGN_DATABASE Indago shows wrong active driver
AVSREQ-184216 ELAB_PERF Build time degradation with oomassoc_opt updates
AVSREQ-179876 LP_1801 Xcelium need to support find_objects -scope with generate block
AVSREQ-177779 RAND_DOC Typo in RNDUNR error message
AVSREQ-100229 ASSERTION_SVA Assertion seems to fail incorrectly if a proceeding consecutive repetition after the implication evaluates to false.
AVSREQ-182010 SIM_CONGRUENCY Congruency: flop qualification issue in presence of if-generate and config file
AVSREQ-178291 DEBUG_DESIGN_DATABASE Incorrect display of nested packed structs and unions
AVSREQ-176939 SIM_PERFORMANCE UCF testcase taking 1000s in cu_post_optimize checkpoint
AVSREQ-172244 SIMVISION_SCHEMATIC simvision schematic loses drag zoom binding
AVSREQ-181807 SIM_PERFORMANCE Continuous assign not working reliably on aarch64
AVSREQ-174439 RAND_DEBUG XGROPENWR during xceligen record
AVSREQ-183875 PARSE_SV INTERR with -parseinfo package
AVSREQ-181699 ELAB_PERF xmelab: *E,SYSTFOR : Builtin system task/function ($finish) is not allowed to override. Use -builtinsystf_allow_override option and recompile.
AVSREQ-179163 RAND_DEBUG INTERNAL EXCEPTION : crash when using enum_var.num in constraints
AVSREQ-178913 SIM_SV Got simulation hang when using -atstar_selftrigger
AVSREQ-154978 XPESSIMISM_GENERAL Support for multiple scopes during Xpess simulation
AVSREQ-177538 POWERPLAYBACK_GENERAL Add POWERPLAYBACK_PRE_TCL_FILE option
AVSREQ-176892 POWERPLAYBACK_GENERAL liberty file list does not accept variable