Mentor Graphics Calibre 2019.1

Mentor Graphics is pleased to announce the availability of Calibre 2019.1. Building on our powerful, production-proven Hyperscaling architecture, Calibre delivers the broadest, most accurate, and best performing DFM solutions in the industry.

About Mentor Graphics Calibre. The chip design lifecyclegoesfrom conceptualizing a logical design to physically manufacturingit on a siliconchip. Most of the semiconductor companies thatdesign chips do not have their own foundries to actually manufacture the chips except for some large semiconductor companies. Eitherway,the design files are handed over from the design teams/organizations to the foundry to perform back-end physical verification, fracturing,and masking of thedesigns on real silicon wafers before theyend up in fabrication.Alldesign organizations perform final physical verificationtasks before the designfiles are sent to the foundries for manufacture. This process is called tapeout. Afterthe foundries receive the GDSII/OASIS files, the filesgo through verification, rule check, pattern matching(PM), optical proximity correction(OPC), and mask data preparation(MDP).Thenthey are finally manufactured in the fabrication units.

Mentor Graphics Calibre is one of the most popular toolsthat is widely used by design organizations and foundries. Calibrehas different modules that perform a variety offunctions post-tapeout. Thechallenge ofthe post-tapeout workflow ismaintaining tight control for high waferyield that would lead to a reduction inthe time-to-mask and operation costs. Whilesome of the workloads from modules such asscatter barand bias in the pre-OPC stage arememory intensive, the workloads generated from PM, OPC,and MDP are latency intensive. They rely on the performance of the storage, network,and computeinfrastructure in ordertosupport and complement the speed and quality of Calibre.

Mentor Graphics Calibre is one of the most commonly usedtools in the silicon on chip (SoC) manufacturing process. This processhandles different parts of the workflow from Calma Graphic Data System (GDSII) to mask flow, providing high wafer yield and reducing the cost of operation. The input files provided from the chip design houses include physical details of SoCsin a GDSIIorOpen Artwork System Interchange Standard (OASIS)format. While Calibreas an application is getting more optimized to reduce the time to mask, the underlying storage infrastructure also plays a significant role on turnaround time (TAT).The infrastructureconsists of network file share storage, the network layer, and the compute farm. NetApp storage is primarily used to store the GDSII/OASIS files and the intellectual property filesin a shared file system accessed by Calibrefrom the compute farm nodes over Network File System(NFSv3).

This video describes the Calibre Automatic Waivers on demand training class, the key concepts that will be covered, and detail covered in the hands-on lab environment.

The Calibre Automatic Waivers tool provides a way for creators of design IP to be able to pass along waived DRC and other types of verification results as waived to the end designers who use the IP. The course is presented from both the viewpoint of the IP designer creating.


Mentor Graphics, a Siemens Business, is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. We enable companies to develop better electronic products faster and more cost-effectively. Our innovative products help conquer complex design challenges. Mentor is technology leader in full chip emulation, Functional Verification, Design-for-Test and physical verification with its Veloce, Questa, Tessent and Calibre platforms.

Product: Mentor Graphics Calibre
Version: 2019.1.29.17 (ixl) *
Supported Architectures: x86_64
Website Home Page : www.mentor.com
Language: english
System Requirements: Linux *
Supported Operating Systems: *
Size: 4.6 Gb