Xilinx Vivado Design Suite 2017.1 HLx Editions

Xilinx, Inc. has released Vivado Design Suite HLx Editions 2017.1. The Vivado HL Design Edition and HL System Edition now support partial reconfiguration. Partial reconfiguration is available for the Vivado WebPACK Edition.

Xilinx partial reconfiguration technology allows you to swap FPGA-based functions in and out of your design on the fly, eliminating the need to fully reconfigure the FPGA and re-establish links. Partial reconfigurability gives you the ability to update feature sets in deployed systems, fix bugs, and migrate to new standards while critical functions remain active. This capability dramatically expands the flexible use of Xilinx All Programmable designs in a truly wide variety of applications.


For example, a detailed article published on the WeChat Web site by Siglent about the company’s new, entry-level SDS1000X-E DSO family—based on a Xilinx Zynq Z-7020 SoC—suggests that the new DSO family’s system design employs the Zynq SoC’s partial-reconfiguration capability to further reduce the parts count and the board footprint: “The PL section has 220 DSP slices and 4.9 Mb Block RAM; coupled with high throughput between the PS and PL data interfaces, we have the flexibility to configure different hardware resources for different digital signal processing.” (See “Siglent 200MHz, 1Gsample/sec SDS1000X-E Entry-Level DSO family with 14M sample points is based on Zynq SoC.”)

In addition, the Vivado 2017.1 release includes support for the Xilinx Spartan-7 7S50 FPGA (Vivado WebPACK support will be in a later release). The Spartan-7 FPGAs are the lowest-cost devices in the 28nm Xilinx 7 series and they’re optimized for low, low cost per I/O while delivering terrific performance/watt. Compared to Xilinx Spartan-6 FPGAs, Spartan-7 FPGAs run at half the power consumption (for comparable designs) and with 30% more operating frequency. The Spartan-7 S50 FPGA is a mid-sized family member with 52,160 logic cells, 2.7Mbits of BRAM, 120 DSP slices, and 250 single-ended I/O pins. It’s a very capable FPGA. (For more information about the Spartan-7 FPGA family, see “Today, there are six new FPGAs in the Spartan-7 device family. Want to meet them?” and “Hot (and Cold) Stuff: New Spartan-7 1Q Commercial-Grade FPGAs go from -40 to +125°C!”)


Now available in the Vivado Design Suite 2017.1:

Vivado Design Suite HLx Editions 2017.1 available now Partial Reconfiguration functionality now included at no additional cost with the Vivado HL Design Edition and HL System Edition. In-warranty users can regenerate their licenses to gain access to this feature.


Additional Updates:

- Production US+ Device Support:
- Zynq UltraScale+ MPSoC: XCZU2EG/CG, XCZU6EG, XCZU9EG/CG
- Kintex UltraScale+: XCKU5P, XCKU9P
- Virtex UltraScale+: XCVU3P
- Public access support for Spartan-7 XC7S50
- Vivado WebPACK support for UltraScale+ XCZU2EG/CG, XCZU6EG and XCKU5P is also enabled
- SDK includes improved boot security, bare-metal application development & debug on XEN hypervisor for Zynq UltraScale+ MPSoC+
- EA availability for SmartLynq Cable: programming and debug cable (powered by Zynq) – 10x faster than Jtag cable

Release notes: HERE

About Xilinx

Xilinx develops All Programmable technologies and devices, beyond hardware to software, digital to analog, and single to multiple die in 3D ICs.A These industry leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration.

Product: Xilinx Vivado Design Suite
Version: 2017.1 HLx Editions
Supported Architectures: x64
Website Home Page : www.xilinx.com
Language: english
System Requirements: PC / Linux
Supported Operating Systems: Windows: 7even / 10 | Linux: Red Hat Enterprise / SUSE Enterprise / Ubuntu / CentOS
Size: 21.3 Gb