Super FinSim ver. 8.1.0

Super-FinSim is the top of the line FinSim Verilog simulator. Ever since the first FinSim Verilog simulator has been sold in 1993, the FinSim Verilog simulators have introduced many new features that have become state of the art in Verilog simulation: mixed Compiled and Interpreted simulation, simulation Farm that allows one engineer to manage hundreds of simultaneous simulations, separate and incremental compilation, high performance save and restart, direct integration with C code without the need for PLI, etc.
Super FinSim supports the entire Verilog standard IEEE 1364-1995 and many features of IEEE 1364-2001, which are listed under Support for Verilog 2001. It's support includes SDF, VCD, PLI, as well as excellent integration with other tools such as a tight integration via API (for better performance than PLI integration) with Debussy and Verdi debug environments from Novas Software, and excellent PLI integrations with Specman from Verisity and Vera from Synopsys for test benches, MMAV from Denali for memory models, Undertow from Veritools for debug environment, HDLScore from Summit Design for code coverage, and others.
In the DA Solution Limited `96 benchmark, the predecessor of Super-FinSim, FinSim-ECS, was rated the fastest Verilog simulator. FinSim was rated the fastest PC-based Verilog simulator in the ASIC & EDA benchmark.
Super-FinSim runs on all popular platforms including Sun Solaris 32 and 64 bit, Linux 32 bit from all providers, Linux 64 bit from Madrake or SuSE, Windows NT/2000, Windows 95/98/ME, and XP.

Note: This version is for Windows Only