Xilinx PlanAhead ver. 8.2.3

Posted By: franklee
Xilinx PlanAhead ver. 8.2.3

Xilinx PlanAhead ver. 8.2.3 | 196 MB
Windows 2000/ XP Pro
PlanAhead – The Fastest Route to Better Design

PlanAhead provides an intuitive environment which delivers a faster, more efficient design solution allowing you to find and fix problems early, helping you achieve your performance goals.

Unmatched Performance

In a recent series of benchmarks, PlanAhead demonstrated an average of 24% faster performance than competing solutions. For more complex, multi-clock designs, the gain jumps to over 50%. This performance edge can reduce project costs with a two speed-grade advantage.

Block-Based, Incremental Design

PlanAhead provides hierarchical, block-based, modular and incremental design methodologies, enabling designers to change only part of the design, leaving placement of the rest intact, thereby shortening design iterations. It helps you consistently maintain the required performance, even while making frequent changes.

Powerful Ease-of-Use

PlanAhead delivers an intuitive environment providing schematic, floorplan, or device views of your design. You can define and refine the hierarchy of your design for better results and more efficient use of resources to achieve optimal performance and greater utilization.

Key Features

ExploreAhead - ExploreAhead, integrated within PlanAhead, is an implementation exploration tool. By managing multiple implementation runs, ExploreAhead allows the user to execute multiple implementation runs based on strategies they’ve defined or predefined strategies shipped as factory defaults.
Signal Integrity - PlanAhead provides functionality to check limits for Weighted Average SSO (WASSO) analysis. This allows designers to more easily limit the amount of ground bounce present immediately at the output of the FPGA and prevent corruption of the operation of other devices driven by the FPGA.

Partial Reconfiguration - PlanAhead simplifies the powerful, yet complex, design flow for partial reconfiguration. Partial reconfiguration is a unique method of changing a dynamic portion of a design while the static portion continues to operate. Partial reconfiguration allows you to reduce the size, weight, cost and power of your design. Users interested in exploring the benefits of Partial Reconfiguration are encouraged to contact their local Xilinx FAE.

TimeAhead - TimeAhead is a flexible timing analyzer integrated into PlanAhead. It allows you to estimate route delays before running place and route. Using the PlanAhead block-based approach, the accuracy of timing estimates will improve as blocks in the design are implemented through place and route.

System Requirements
Microsoft Windows 2000 and XP Professional

Device Family Support
Virtex-5 LX
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-II Pro

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