Cadence CONFORMAL 19.10.100

LEC:
1166481 four nonequivalent DFFs due to clock gate modeling
1232960 reporting not mapped latches which are unreachable
1452297 support MB mapping file
1471339 LEC pin constraint issue
1481054 simulation library with vdd vss pin causing mapping problem (multibit mapping)
1485654 14.10-p100 crash during 'read design' and parsing error in 15.1
1493449 15.1 false floating signal due to systemverilog design modeling issue
1498246 stuck at elab design
1524866 what causes Mismatches - tool or design?
1538130 "read design -define …" is not reported in VLG9.2
1549116 report all parse error in one shot
1549813 crash during flattening
1575106 catch elaborate design error
1609967 crash
1611221 incorrect function based Mapping in multibit flop design
1620934 rtl struct to netlist port matching when reading design does not seem to happen
1625859 display pin constraint on schematics
1626361 disable -continuousassignment unidirection in LP-EC
1626714 hier compare enhancement request
1632584 read with -sv is not creating implicit wire
1652712 add notranslate lines switch -both not valid
1665853 conformal license checkout failed
1689872 RTL7.16
1694737 seeing system verilog parse error with "integer ar[]" in function
1699401 crash during elaboration
1701082 PARSE ERROR on libs during LEC
1701902 falsely reports a syntax error due to a name collision between the package name "noise" and a variable "noise"
1715827 need "gate class" gui option in mapping manager
1717259 lef report "parse error, expecting IDENTIFIER near token '= '
1718680 uniquify to use internal renaming rule
1729338 false CPF_LIB5 on power switch cell with netlist_style logical
1736163 enhancement request for reporting keypoint name after application of multi-bit options
1736683 add partition point to solve abort gives noneq
1752742 crash While modeling revised design
1766222 segmentation fault (core dumped)
1783382 parsing error in non-constant parameter
1826242 not detecting the parameterized flops till the parameters are replaced with literals
1829525 crash while running analyze xortree
1836751 incorrectly sign-extends an operand in an expression that is overall unsigned
1840672 does not compute the $floor system function correctly
1858130 request for two enhancements (Search by Gate ID in simplified Schematics and reporting Library cell via Gate ID)
1861314 enhancement in donotmap_pattern
1862344 treats 'unique if' different from Genus results in false NEQ
1870241 results in nonEQ comparing SV to HDLICE netlist
1892527 elaboration error when reading a .sv file for Conformal LEC tool
1893376 phase mapping issue
1906440 enhancement needed for instances which are NOT bound by using cfg files
1917887 enhancement request for reporting mapped and unmapped points after setup analysis
1933611 document reporting nonEQ points from analyze_project -hier_to_flat
1944531 RTL to netlist noneqs due to a not-mapped flops coming up in Golden side
1945869 systemverilog macro expansion in conformal differs to other tools(e.g. incisive)
1951758 seq const verification causing tool crash
1968985 Intel-Polaris: Not-mapped Z gates in the latest release
1971015 elaboration issues with latest version 18.10-s200
1973810 elaboration issues with latest version 18.10-s200
1977051 crash while using command report modules
1981557 genus flow aborts
1981618 set_flatten_model -CG_CLOCK_INPUT_LIST not working when partition netlist has more than one spine input port
1983747 run is stuck at elaboration
1992834 crash while reading golden power intent
1994189 crashes during parsing
1994583 add note with extract_info_to_file option in the command reference
1994761 crash during datapath analysis in RTL to initopt run in 18.1.s300 version
1995412 erroneous handling of VHDL constant
1996816 LEC 18 stopping parsing the source file when a warning is encountered
1996867 v2k cfg for arrayed instances is not being honored as per LRM
1997585 elaboration issues with latest daily build(18.10-d333) which is not seen 18.10-d305
1998033 ECO stuck at modelling stage
1998852 read_library doesn't accept parameters as typedef array indices in packages
2000801 issue with analyze project -hier_to_flat
2003366 18.10 fails to elaborate sv rtl that elabs in Genus preventing EC.
2005057 Why is asynch reset input brought into this cone of logic?
2007843 internal error when open fanout on MBIT cell in "Copy Schematic"
2007849 clamp-0 isolation cell where iso enables get swapped between golden and revised
2011991 limit dynamic flatten
2012791 crash during Read design
2012865 read design parsing error not expected
2013631 crash during Liberty parsing
2015506 conformal crash on encrypted RTL
2017902 Scan setting check at earlier stage
2017912 'analyze module' takes a long runtime when CPF is read
2019003 enhancement request to check the primary (Bus) ports between Gold and Rev for consistency
2019360 read design tool crash during elab
2020071 elab error causing module to be blackboxed
2020078 conformal is not implicitly implying the ?? operator
2020376 ECO debug, LEC is EQ in hier and non eq in flat
2022028 fails with simple SystemVerilog import package construct
2022947 option to "write design" without "assign" statement
2024835 command "abstract_logic" takes 26 hours long
2030153 18.20-s200 not available on InstallScape
2032145 does not honor multi-thread through write hier dofile -compare_string "dofile compare.do"
2033311 add pin binding does not auto map all pin bindings
2034465 partition EQ in 18.20-p100 and NEQ in 18.20-s200
2035068 elab design gave bogus warnings on config file
2035146 add pin binding did not work for module write-out in write hier
2038841 testcase packager - strace times out during strace.out generation
2039662 modeling of partial sum DW02_multp is blocked by power pin
2039759 crash during datapath analysis
2040166 partition is getting stuck at modelling
2042604 unsupported covergroup/coverpoint produces error when it should be ignored
2042777 stuck at flattening/modeling over 8 hours and counting
2043372 different tool version yielded different quality in analyze datapath
2044485 does not understand clock gater
2045779 abstract_gated_clock error: Array size 2147483647 beyond the max threshold
2046483 enhance usability of CheckPoint - threading and tmp directory enhancement
2048979 crash with flowgraph datapath algorithm
2050176 getting error writing blackbox wrapper with recent version 18.2-s300
2052139 false EQ by hier compare caused by unnecessary output_z modeling
2054348 elab crash in 18.20-s300 while not in 17.20
2056589 high runtime in 18.20 but much less in 17.20
2056908 crash during revised modeling for g2g run
2057480 enhance to print out DW path once "set dw option -dw_mult_div"
2057522 enhance to automatically include unreachables in sequential constant compare mode
2057530 mdp analysis complained no DP_OP, but they are present
2058868 long runtime at "Automatic analyze setup" step in a CECO run
2059188 smart LEC is getting stuck during module comparison at go_hier
2061994 18.20-s300 crashes during verilog rtl read_design -golden.
2062964 crash during smart lec while normal lec run completes with aborts
2065999 analyze setup crashed when "add donttouch registers" is used
2066536 datapath analysis performance issue
2067471 command example typo in Conformal User Guide 18.2
2067758 crash during golden design elaboration due to “set_naming_style rc” command
2070320 18.20-s300 & latest daily build crashing during elaboration
2070349 18.20-s300 elaboration failure
2072506 smart LEC document error
ECO:
1213148 crash while running “compare eco hierarchy”
1396737 scan SI path broken
1564159 ECP flow hang for 10 days
1622664 there are l errors during patch generation
1638165 why tie scan mode to zero on clock gate?
1648349 G3vsG2 is noneq
1680651 ECO patch touching scan logic
1710835 questions on command "add spare cell -cell"
1910034 generating incomplete patch
1951744 error executing ecopins.do
1972197 generates syntax error eco net
2031001 getting noneq after analyze_eco patch application
2032868 -noadd_icg does not seem to work
2044814 misses sequential constant in first pass ECO
2046644 hier-fef issues
2055510 why ECO is placing MUX instead of a BUF in patch generated
2056059 long runtime at "compare_eco_hier" stage
2059565 options "-cone_swap" and "-cone_swap_file" causes crash
2060460 long "compare_eco_hier" runtime
2069378 compare eco hier taking a long time
2069834 crash during ECO run during analyze eco
2071755 noneq count increased after apply patch command
CLP:
1328818 modification of CPF_HIER_MAP10 and new CPF_HIER_MAP10a
1364357 understand logic equation on shutoff condition signals
1486453 report error on combo cell with invalid location
1489043 missing STRATEGY_SUPPLY_SET_CONFLICT_ISO
1515126 check macro nominal voltage against what's specified in 1801 file
1553878 pwr switch cell control pin
1564350 Error: (STRATEGY_ACK_CONN_CONFLICT) Switch acknowledge receiver net is not asserted
1567624 crash while running compare power consistency
1571081 high runtime while reading revised power intent
1571693 read power intent -insert_isolation hangs
1593584 request for the support of supply port equivalence
1668873 CPF_PSO9 expects a shutoff condition that is not correct
1675163 LPEC reports noneq with add notranslate module and Eq with add black box
1823997 crashes during elaboration
1863629 conversion of "message based" waivers to "tcl based" waivers
1922926 collision with TCL variables when two UPFs (golden & revised) with internal and external variables are read in
1924037 ground pin vss reporting a pin constraint 1
1948859 UPF find_objects not giving expected output for interfaces
1967068 request documentation for compare power grid
2004761 support for define_power_model/apply_power_model
2007845 non-retention op merged into a retention MBF(or vice-versa)
2011103 single power cell output without related_power_pin need to check crossing
2011226 LPEC fails to insert power ports on level shifter
2011322 isolation cells is not inserted correctly and result in self loop
2017643 report all the power intent files read in by Conformal
2018930 support for apply_power_model -port_map to a constant
2019770 check inconsistency between macro's base_domains and upper base_domains
2023107 enhancement for power grid report
2023114 report to see what got ignored during the power grid comparison
2025443 LS1a error in post-integrated CPF analysis but not in pre-integrated CPF analysis
2031458 help in understanding CPF_LS1a behavior when LSH is present or not on the domain crossing driven by a constant
2036220 document 'checkpoint' command in LowPower_Ref.pdf
2040938 what could cause LSH3 violation on Power switch output?
2042553 physical netlist does not work with internal supply (1801_REF_OBJ_NOT_FOUND).
2043316 flagging "STRATEGY_CTRL_CONN_CONFLICT_PSW" on mother-daughter power switch cell
2044529 incorrect occurrences of ISO_EN_INACTIVE_REDUNDANT_MACRO on RTL
2046477 linter support for constants on apply_power_model -port_map
2046936 merge of any instance type on power grid for compare power grid
2046942 create_logic_port not creating Implicit net
2047089 unable to understand a connect_logic_net which is in a scope different from the top scope
2049601 creates a gray box without any explanation
2055157 false 1801_STRATEGY_ELEMENT_INOUT messages
2055273 does not seem to recognize lower level power domain style states
2059801 right way to describe a virtual supply net in UPF?
2063318 1801_REF_SUPPLY_UNASSOC for default_isolation handle
2066853 apply_power_model -port_map is not making proper connections
2068883 PIC set_port_attribute NEQ when -pic_renaming option is enabled
2070032 false error on missing clamp_value when set_isolation -update is used
2071964 reporting Error 1801_LINT_OPT_MISSING_MANDATORY for option clamp_value
2073273 rule check to report missing top-level set_port_attribute -driver/receiver supply
CCD:
1687350 RTL7.16 error not accounted for
1689755 run_rule_check hangs without dumping report
1756645 check for generated clock and its corresponding Master clock
1756656 new rule for Sequential reconvergence
1756669 check to consider clock/set/reset pins and constant propagation
1756670 CCD_CLK_DEF6 (not cover clock gating cell clock pin)
1756675 needs to be "timing check" aware in the same way as Tempus
1756691 enhance to have check_timing -check_only clock_missing_at_sequential_output check
1756693 enhance to have check_timing -check_only data_check_multiple_reference_signal check
1756695 enhance to have check_timing -check_only data_check_no_reference_signal check
1989166 encrypted Chipware components should be read by default in CCD as done in Genus
2029184 error when version 2.1 is provided with read_lint_configuration
2042089 redirection is not working
2048264 enable custom user schemes only
2051307 incorrect behavior for get_lib_pin - and no Error/Warning
2055769 crashes as soon as user opens the Rule Manager after run_rule_check

Supported Platforms
–––––––––-
Conformal products run on most major UNIX workstations.

X86_64 : RHEL 6 and 7 (64 bit) : SLES 11 and 12 (64 bit)

Supported Design Formats
––––––––––––
- Verilog (RTL and gate-level)
- System Verilog
- VHDL (RTL and gate-level)
- EDIF
- NDL
- SPICE (CMOS)

Supported Library Formats
––––––––––––-
- Verilog
- VHDL
- Liberty