Synopsys VCS vQ-2020.03-SP2-7 | 4.2 Gb
Synopsys, Inc., the technology leader for complex IC design, has unveiled VCS vQ-2020.03-SP2-7, the next release of the industry's highest performance Verilog simulator.
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Synopsys VCS vQ-2020.03-SP2-7
Date: 27 Feb 2023 09:26:33
Synopsys, Inc., the technology leader for complex IC design, has unveiled VCS vQ-2020.03-SP2-7, the next release of the industry's highest performance Verilog simulator.
Aldec Active-HDL 13.0.375.8320
Date: 29 May 2022 11:15:59
Aldec Active-HDL 13.0.375.8320 | 577.5 mb
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, advances VHDL’s verification capabilities with Active-HDL, version 13.0. This latest release introduces support for VHDL-2019 protected types with generics, composites of protected types, pointers to objects of protected types and composition with protected types.
Aldec ALINT-PRO 2021.09
Date: 7 Feb 2022 14:59:11
Aldec ALINT-PRO 2021.09 | 904.0 mb
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched ALINT-PRO 2021.09 is design rule checking (DRC) tool, which decreases development time dramatically by identifying design issues early in the development schedule.
Cadence XCELIUM version 19.09.001
Date: 28 Nov 2021 14:40:50
Cadence XCELIUM version 19.09.001 | 8.6 Gb
Updated: Reupload due to fatal CRC error. Please download all blocks.
Thank you for understanding.
Updated: Reupload due to fatal CRC error. Please download all blocks.
Thank you for understanding.
Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled XCELIUM 19.09.001 is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.
Cadence CONFORMAL 19.10.100
Date: 5 Nov 2021 15:53:29
Cadence CONFORMAL 19.10.100 | 1.2 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled CONFORMAL 19.10.100. This technologies provide you with an independent equivalence checking solution enabling verification of designs from RTL to final netlists from P&R.
Mentor Graphics QuestaSim 2021.2.1 Linux
Date: 10 Oct 2021 17:50:43
Mentor Graphics QuestaSim 2021.2.1 Linux | 3.8 Gb
Mentor, a Siemens business, is pleased to announce the availability of QuestaSim 2021.2.1 comprehensive platform for verification complex designs, is the core simulation and debug engine of the Questa Verification Solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.
Aldec Active-HDL 12.0.118.7745
Date: 17 Feb 2021 17:41:17
Aldec Active-HDL 12.0.118.7745 | 550.4 mb
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has enhanced Active-HDL to support new features within VHDL-2019 (IEEE 1076-2019). These features simplify the language, lift certain restrictions that were present in earlier versions and introduce new application programming interfaces (APIs).
Mentor Graphics ModelSim 2020.4
Date: 28 Dec 2020 12:35:05
Mentor Graphics ModelSim 2020.4 | 4.9 Gb
Mentor, a Siemens business, is pleased to announce the availability of ModelSim 2020.4, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment.