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Xilinx Vivado Design Suite HLx Editions 2020.2

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Xilinx Vivado Design Suite HLx Editions 2020.2

Xilinx Vivado Design Suite HLx Editions 2020.2 | 47.7 Gb

Xilinx, Inc. announced the Vivado Design Suite HLx Editions 2020.2, enabling a new ultra high productivity approach for designing All Programmable SoCs, FPGAs, and the creation of reusable platforms.

Vivado Design Suite HLx Editions 2020.2 - Date: Nov 24, 2020

Device Support
- Versal AI Core series : XCVC1902 and XCVC1802
- Versal Prime Series : XCVM1802
- Zynq UltraScale+ RFSoC: XCZU43DR, XCZU46DR, XCZU47DR, XCZU48DR, XCZU49DR

Install and Licensing
- Petalinux is now a part of the Xilinx Unified installer in addition to the existing standalone installation offering.

IP Integrator

Revision Control Improvements
- New directory structure separating sources from output products
- BD/IP output products are no longer placed in the project.srcs directory.
- All output products reside in the project.gen directory parallel to the project.srcs.
Address Map Enhancements
- Graphical view of Address Map in HTML
Vitis Platform Creation Improvements
- Ability to identify Vivado Project as an extensible platform project during Project Creation and in Project Settings​
- Add new Platform Interface validation DRCs
- Run Platform DRCs during validation for platform BDs​
- New Platform Setup GUI​
IP Caching improvements​
- Ability to create and use Read-Only zipped IP Caches ​
- Zipped Cached can be pointed to and need not be unzipped
Block Design Container
- Instantiate a BD inside another BD​
CIPS (Control, Interfaces and Processing System) – Versal
- Example Designs in XHUB stores – Versal ​

IP Enhancements

Data Center

Queue DMA Subsystem for PCI Express (QDMA) device support expansion
- Gen3x8 in "-2LV" UltraScale+ devices
- Gen4x8 in "-2LV" Virtex UltraScale+ VU23P device
Versal ACAP subsystems for PCI Express targeting GTY, PL PCIE4, and CPM4 integrated blocks
- Integrated Block for PCI Express (GTY + PL PCIE4)
- DMA and Bridge Subsystem for PCI Express (GTY + PL PCIE4 + Soft QDMA, XDMA, AXI-Bridge)
- CPM Mode for PCI Express (GTY + CPM4)
- CPM DMA and Bridge Mode for PCI Express (GTY + CPM4 + Hard QDMA, XDMA, AXI-Bridge)
- PHY for PCI Express (GTY)

Video and Imaging

- DPHY rates on Versal devices increased: 3200Mbs on -2 and -3 devices, 3000Mbs on -1 devices
- Added YUV420 output support for CSI RX core
DisplayPort 1.4 Subsystems
- YUV420 support, Adaptive sync, Static HDR
- eDP IP option in general access
SDI subsystems
- HLG HDR support
- Versal VCK190 pass thru example design
HDMI2.0 adds support for HDCP2.3

Wired and Wireless
- JESD204C Full Production
- New 200G RS-FEC for UltraScale+ and Versal
- 1G/10G/25G Ethernet adds 1-step and TSN support
- Versal MRMAC 1-step 1588 hardware timestamping​
- 10G/25G MRMAC Ethernet 2-step 1588 linux driver support ​


New ERNIC features
- resource optimizations for 100G sustained bandwidth support
- support for the new VU23P device
- Improvements to Priority Flow Control (PFC)
NVMeTC now supports the new VU23P device
Lossless Compression IP, GZIP and ZLIB algorithms
NVMeOF Reference Design now available for both Alveo U50 and Bittware 250-SoC boards


- XPM_CDC is now available through IPI
- URAM Initialization Support for Versal
Infrastructure and Embedded
- New SmartConnect features
. Priority arbitration
. Low area mode
EMG (Embedded Memory Generator) in IPI for Versal, replacing Block Memory Generator
EFG (Embedded FIFO Generator) in IPI for Versal, replacing FIFO Generator


Wizards now available for Versal
- GTY Transceivers Wizard
- Advanced IO Wizard
- Clocking Wizard
New Transceiver Wizard features
- Full Block Automation, with lane selection
- On-the-fly reconfiguration (Versal only)
- Quad sharing (Versal only)
- Transceiver Bridge IP (Versal only)
High level Synthesis
- Vitis HLS replaces Vivado HLS in Vivado (was already default for Vitis in v2020.1)
- Adds array reshape and partitioning directives for top ports
- Simplified toolbar icon layout with new reporting sections for interfaces and AXI-4 bursts
- Inference for single clock cycle floating point accumulation in DSP blocks for Versal
- Tcl files can create a project and open it in the GUI directly (vitis_hls -p <file>.tcl)
- New single click filter for non-default options in “Solution Settings”→”General”
- Constrained random testing for AXI interfaces now visible in the GUI
- On-chip block RAM ECC flags option via the bind_storage pragma
- Interactive FIFO depth sizing in GUI during CoSim
- Support for SIMD programming (vector data types)

Add-on for Matlab & Simulink
- Unified installer will give them both Model Composer and System Generator in one launcher


VHDL-2008 support
- Shift Operators (rol, ror, sll, srl, sla and sra)
- Mixing Array and Scalar Logical Operators
- Conditional Sequential Assignments on signal
- Case Generate
- Extensions to Globally Static and Locally Static Expressions
- Static Ranges and Integer Expressions in Range Bounds
Support for cross language Hierarchical name
- Verilog hierarchical name will be enabled to access VHDL signals from SV/Verilog modules
Simulator support for Versal
- Xilinx Simulator
- 3rd party Simulators
. Cadence Xcelium
. Mentor Graphics Questasim

Hardware Debug
- Versal AXIS-ILA
- Debug flow improvements
- Debug block automation improvements
- Support for selecting URAM and AXIS-ILA trace storage

- Support for System Verilog string type
- Fixed and floating-point package support in VHDL-2008
- Automatic pipelining for heterogeneous RAMs
- Logic Compaction directive is extended to Versal LOOKAHEADs

Implementation Design Flow
- Placer replication (PSIP) improvements
- Power rail definition and power analysis
- BUFG-to-MBUFG global buffer conversion (Versal)

Design Analysis and Timing Closure
- RQA and RQS improvements

Dynamic Function eXchange (DFX)
- Abstract Shell for Dynamic Function eXchange
- Isolation design flow(IDF) + DFX in one design

The Vivado Design Suite offers a new approach for ultra high productivity with next generation C/C++ and IP-based design along with more traditional languages such as VHDL and Verilog.

The new HLx editions supply design teams with the tools and methodology needed to leverage C-based design and optimized reuse, IP sub-system reuse, integration automation and accelerated design closure. When coupled with the UltraFast High-Level Productivity Design Methodology Guide, this unique combination is proven to accelerate productivity by enabling designers to work at a high level of abstraction while facilitating design reuse.

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs, and 3D ICs. Xilinx uniquely enables applications that are both software defined and hardware optimized – powering industry advancements in Cloud Computing, SDN/NFV, Video/Vision, Industrial IoT, and 5G Wireless.

Product: Xilinx Vivado Design Suite
Version: HLx Editions 2020.02 *
Supported Architectures: x64
Website Home Page : www.xilinx.com
Language: english
System Requirements: PC / Linux **
Size: 47.7 Gb




Supported Operating Systems

Xilinx supports the following operating systems on x86 and x86-64 processor architectures.

- Microsoft Windows Professional/Enterprise 10.0 1809 Update; 10.0 1903 Update; 10.0 1909 Update; 10.0 2004 Update
- Red Hat Enterprise Workstation/Server 7.4 - 7.8, and 8.2 (64-bit), English/Japanese
- CentOS 7.4 - 7.8, and 8.2 (64-bit), English/Japanese
- SUSE Linux Enterprise 12.4 (64-bit), English/Japanese
- Amazon Linux 2 AL2 LTS (64-bit)
- Ubuntu Linux 16.04.5 LTS;16.04.6 LTS; 18.04.1 LTS; 18.04.2 LTS, 18.04.3 LTS; 18.04.4 LTS;and 20.04 LTS (64-bit), English/Japanese

Installation Requirements
The PetaLinux tools installation requirements are:

• Minimum workstation requirements:
8 GB RAM (recommended minimum for Xilinx tools)
2 GHz CPU clock or equivalent (minimum of eight cores)
100 GB free HDD space

Supported OS:
- Red Hat Enterprise Workstation/Server 7.4, 7.5, 7.6, 7.7, 7.8 (64-bit)
- CentOS Workstation/Server 7.4, 7.5, 7.6, 7.7, 7.8 (64-bit)
- Ubuntu Linux Workstation/Server 16.04.5, 16.04.6, 18.04.1, 18.04.2, 18.04.3, 18.04.4(64-bit)
• You need to have root access to install the required packages mentioned in the release notes.The PetaLinux tools need to be installed as a non-root user.
• PetaLinux requires a number of standard development tools and libraries to be installed onyour Linux host workstation. Install the libraries and tools listed in the release notes on thehost Linux.
• PetaLinux tools require that your host system /bin/sh is 'bash'. If you are using Ubuntudistribution and your /bin/sh is 'dash', consult your system administrator to change yourdefault system shell /bin/sh with the sudo dpkg-reconfigure dash command.

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Xilinx Vivado Design Suite HLx Editions 2020.2