Verilog HDL: a guide to digital design and synthesis
Verilog HDL: a guide to digital design and synthesis By Samir Palnitkar
2003 | 261 Pages | ISBN: 0130449113 | PDF | 8 MB
2003 | 261 Pages | ISBN: 0130449113 | PDF | 8 MB
Verilog HDL is a language for digital design, just as C is a language for programming. This complete Verilog HDL reference progresses from the basic Verilog concepts to the most advanced concepts in digital design. Palnitkar covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, switch level modeling, PLI, and logic synthesis. Verilog HDL is a hardware description language (with a user community of more than 50,000 active designers) used to design and document electronic systems. This completely updated reference progresses from basic to advanced concepts in digital design, including timing simulation, switch level modeling, PLI, and logic synthesis.