Systemverilog/Uvm For Asic/Soc Verification Part 2

Advanced SystemVerilog/UVM Concepts Explained using AMBA-AHB Protocol

What you'll learn

Mastering the UVM Fundamentals in advanced contexts

Testbench Architecture design - Integrating various UVM Components to create a robust and reusable verification environment

Protocol Specific Knowledge and Application related AHB

Transaction Level Modelling and Analysis

Debugging and Optimization Skills

UVM Register Abstraction Layer

Requirements

Digital Electronics

Logic Design Flow

SystemVerilog

Advanced Programming Knowledge

Description

Mastering UVM for ASIC/SoC Verification with QuantSemicon: From Fundamentals to Industrial ApplicationsAre you ready to unlock the full potential of the Universal Verification Methodology (UVM) and elevate your design verification skills to an industrial level? This comprehensive course, developed by QuantSemicon’s expert team, is designed for both beginners and advanced learners who want to master UVM for ASIC/SoC verification. With a hands-on approach and real-world examples, this course will take you from the fundamentals of UVM to advanced methodologies, preparing you for the challenges of the semiconductor industry.What You’ll Learn:UVM Basics: Begin your UVM journey by understanding the core components and architecture. Learn about UVM testbenches, agents, sequences, and how UVM standardizes verification environments across projects for scalability and reusability.UVM Testbench Architecture: Understand how UVM organizes a verification environment with components like the driver, monitor, and scoreboard. Learn to build modular and reusable testbenches that improve efficiency in verification.Hands-On Industrial Examples: Gain practical experience with real-world projects. This course provides detailed examples such as verification environments for protocols like the Advanced Peripheral Bus (APB), preparing you to handle industrial-scale UVM projects. You will also explore in-depth verification scenarios for AHB, AXI, and RISC-V in future modules.Transaction-Level Modeling (TLM) in UVM: Learn how TLM simplifies communication between components, allowing you to build flexible, scalable verification architectures that are used in complex SoC and ASIC projects.Quizzes & Assessments: Each module includes quizzes to ensure you’ve absorbed the material and are ready to move to the next level. These interactive assessments are designed to solidify your knowledge and keep you on track.Advanced UVM Features: As you progress, dive deeper into advanced UVM features like the UVM Register Abstraction Layer (RAL), UVM factory, virtual sequences, and configuration management, preparing you for complex verification challenges.SystemVerilog Integration: Throughout the course, you’ll learn how UVM integrates seamlessly with SystemVerilog, leveraging its object-oriented programming features, assertions, and randomization techniques to create powerful and efficient testbenches.Course Highlights:Comprehensive UVM Coverage: From basic to advanced UVM concepts, including transaction-level modeling, agents, sequences, and more.Real-World Examples: Every concept is reinforced with industrial examples, giving you confidence to apply UVM to real-world projects.Modular and Reusable Testbenches: Learn to create scalable verification environments for complex designs.Interactive Quizzes & Assessments: Test your understanding with quizzes and exercises after each module.Future-Ready Knowledge: Prepare for advanced UVM concepts such as UVM RAL and virtual sequences.By the end of this course, you will have a robust understanding of UVM, hands-on experience building scalable testbenches, and the skills to tackle complex verification challenges in the industry.Whether you are a student preparing for a career in the semiconductor industry or a professional looking to advance your verification skills, this course provides a structured path to mastering UVM. Join us and take the first step toward becoming a UVM expert!

Overview

Section 1: SystemVerilog Coverages

Lecture 1 SystemVerilog Coverage

Lecture 2 Functional coverage and its implementation

Lecture 3 Functional coverage-Syntax

Section 2: SystemVerilog Assertions

Lecture 4 SystemVerilog Assertions

Section 3: Transaction Level Modelling Concepts

Lecture 5 TLM Communications

Lecture 6 What is TLM & TLM Interfaces

Lecture 7 Basic TLM Communication

Lecture 8 Put vs Get

Lecture 9 FIFO's

Lecture 10 Analysis Port

Section 4: Introduction AHB Protocol

Lecture 11 AHB Protocol part 1

Lecture 12 AHB Protocol Part 2

Lecture 13 Overview of AHB operation

Lecture 14 AHB - Simple Transfer

Lecture 15 AHB - Transfer with wait states

Lecture 16 AHB - Transfer type and Example

Section 5: Summary of Introduction to UVM and UVM Components​

Lecture 17 Introduction to UVM & UVM Components

Lecture 18 Introduction to UVM & UVM Base

Lecture 19 What is UVM?

Lecture 20 Key Features of UVM

Lecture 21 Goal of UVM

Lecture 22 UVM Testbench Architecture

Section 6: Component Configuration and Factory Registration​

Lecture 23 Setting up the Environment

Section 7: UVM Phases and Processes

Lecture 24 Understanding the UVM Phases

Section 8: UVM Testbench Architecture​

Lecture 25 Introduction to UVM Testbench Architecture

Lecture 26 Structural Component vs Stimulus generation

Lecture 27 Inheritance in UVM

Lecture 28 UVM Testbench block diagram and UVM Top

Lecture 29 UVM_Test

Lecture 30 UVM Environment

Lecture 31 Universal Verification Components

Lecture 32 UVM_Agent

Lecture 33 Sequencer

Lecture 34 Driver

Lecture 35 Monitor

Lecture 36 Scoreboard

Section 9: UVM Sequences and Transactions​

Lecture 37 Introduction to UVM Sequences & Transactions

Lecture 38 Sequence Class

Lecture 39 Generate Transactions in Sequence Class

Lecture 40 User Can Manually Create and Send Item

Lecture 41 uvm_do macro

Lecture 42 uvm_rand_send macro

Lecture 43 uvm_create macro

Lecture 44 uvm_do_with macro

Lecture 45 uvm_do_pri macro

Lecture 46 uvm_do_pri_with macro

Lecture 47 uvm_send_pri macro

Lecture 48 uvm_rand_send_pri macro

Lecture 49 uvm_rand_send_pri_with macro

Lecture 50 Structural Components vs. Stimulus Generation

Lecture 51 uvm_do macro: Interaction Detailed

Lecture 52 UVM Inheritance

Lecture 53 Sequence Execution: Starting a Sequence

Lecture 54 UVM_Testbench_top

Lecture 55 start() method in Sequence Class

Lecture 56 Sequence Execution Methodologies

Lecture 57 Explicit Sequence Execution

Lecture 58 Implicit Sequence Execution

Lecture 59 UVM Sequencer

Lecture 60 UVM Sequencer: Example

Lecture 61 Driver Sequencer Handshake

Lecture 62 How the Handshake works

Lecture 63 Virtual Sequence

Lecture 64 Virtual Sequencer

Lecture 65 Example: Virtual Sequencer

Lecture 66 Arbitration in UVM_Sequencer

Section 10: UVM Testbench Debugging Techniques​

Lecture 67 UVM Reporting

Section 11: AHB based Project Work and Review​

Lecture 68 AHB Testbench from Scratch

Bachelor of Technology, Bachelor of Engineering,Anyone Interested in Semiconductor,Master of Technology,Students: Electronics, Microelectronics, VLSI, Embedded,Working Professionals : VLSI design professional, Verification Engineers, Verification Leads