Communication Series P3 : Amba Axi In Verilog

Step by Step Guide from Scratch

What you'll learn

Essential principles of AXI Stream, AXI Lite and AXI Full.

Implementation of AXI Stream, AXI Lite and AXI Full master and slave from scracth.

Implementation of AXI Burst modes in Verilog.

Implementation of AXIS Arbiter, AXIS FIFO and AXI Lite GPIO from scratch.

Requirements

Basics understanding of Verilog and Digital Electronics

Description

AXI (Advanced eXtensible Interface) is widely used in System-on-Chip (SoC) designs because it provides a highly efficient and flexible interconnect solution for complex systems.Master the essentials of the AXI protocol with our hands-on course, designed to provide in-depth knowledge of AXI fundamentals in Verilog. With 95% coding and only 5% theory, the focus is on practical, real-world skills. You will explore the signals of AXI Stream, AXI Lite, and AXI Full interfaces and build AXI Master and Slave components from scratch. Learn to implement various burst modes, verify AXI transactions using the AXI protocol checker, and design advanced components like AXI Stream FIFOs, arbiters, and AXI Lite GPIO modules. The course emphasizes coding practice while offering essential theoretical insights to strengthen your understanding of AXI’s intricacies. Ideal for design and verification roles, this training equips you with the skills to excel in your career and confidently tackle challenging interviews. Whether you're a beginner or an experienced professional looking to sharpen your expertise, this course provides a comprehensive learning experience. In addition, you'll gain exposure to real-world applications of AXI in complex systems, enhancing your ability to design, debug, and verify AXI-based solutions. Enroll now to gain the knowledge and hands-on experience needed to master AXI in Verilog and take a significant step forward in your VLSI journey.

Overview

Section 1: Introduction

Lecture 1 Agenda

Lecture 2 Used cases of different AXI interfaces

Lecture 3 Differences in Interfaces pins

Lecture 4 Simple Memory Vs AXI memory

Lecture 5 Understanding Valid Ready Handshake

Lecture 6 Valid Ready Handshake rules

Lecture 7 Implementing Valid Ready Handshake P1

Lecture 8 Implementing Valid Ready Handshake P2

Lecture 9 Verifying Operation of code

Lecture 10 Code

Section 2: AXI Stream Interface Fundamentals

Lecture 11 Agenda

Lecture 12 Typical AXI Stream Signals P1

Lecture 13 Typical AXI Stream Signals P2

Lecture 14 Used Cases of AXI Stream Interface

Lecture 15 AXI stream transactions

Lecture 16 Ways to implement AXI Interface

Lecture 17 Fundamentals of AXI Stream transactions / waveforms P1

Lecture 18 Fundamentals of AXI Stream transactions / waveforms P2

Lecture 19 Fundamentals of AXI Stream transactions / waveforms P3

Lecture 20 Building AXIS Master

Lecture 21 Verifying Operation of Master

Lecture 22 Code

Lecture 23 Building AXIS Slave P1

Lecture 24 Building AXIS Slave P2

Lecture 25 Verifying AXIS Slave Operation

Lecture 26 Code

Lecture 27 Connecting Master and Slave Together

Lecture 28 Code

Section 3: Using AXI Stream Interface for building IP's

Lecture 29 Agenda

Lecture 30 Understanding Round Robin Arbiter P1

Lecture 31 Understanding Round Robin Arbiter P2

Lecture 32 Understanding Round Robin Arbiter P3

Lecture 33 Code

Lecture 34 Implementing AXIS Arbiter P1

Lecture 35 Implementing AXIS Arbiter P2

Lecture 36 Implementing AXIS Arbiter P3

Lecture 37 Verifying Operation of DUT

Lecture 38 Code

Lecture 39 Implemneting AXIS FIFO P1

Lecture 40 Implemneting AXIS FIFO P2

Lecture 41 Implemneting AXIS FIFO P3

Lecture 42 Code

Lecture 43 AXIS FIFO alternate implementation

Lecture 44 Code

Section 4: Getting Started with AXI Lite

Lecture 45 Agenda

Lecture 46 transaction vs beat vs transfer

Lecture 47 Understanding Write address channel

Lecture 48 Understanfing Channel ID's

Lecture 49 Understanding Write data channel

Lecture 50 Understanding Write response channel

Lecture 51 Different types of response

Lecture 52 Understanding read address and data channel P1

Lecture 53 Understanding read address and data channel P2

Lecture 54 AXI Lite Signals

Section 5: Single Beat without Pipeline : AXI Lite with Waveform based approach

Lecture 55 Agenda

Lecture 56 Different AXI configurations

Lecture 57 Implementation approaches : Waveform vs FSM

Lecture 58 Signals in Single beat without pipeline P1

Lecture 59 Signals in Single beat without pipeline P2

Lecture 60 I/O ports in Single beat without pipeline

Lecture 61 AXIL Master with only write Implementation P1

Lecture 62 AXIL Master with only write Implementation P2

Lecture 63 AXIL Slave with only write Implementation P1

Lecture 64 AXIL Slave with only write Implementation P2

Lecture 65 Verifying Operation of Master and Slave with only write

Lecture 66 Design Code

Lecture 67 TB Code

Lecture 68 Validating transactions with AXI Protocol Checker P1

Lecture 69 Validating transactions with AXI Protocol Checker P2

Lecture 70 Validating transactions with AXI Protocol Checker P3

Lecture 71 Design Code

Lecture 72 TB Code

Lecture 73 AXIL Master with only read Implementation P1

Lecture 74 AXIL Master with only read Implementation P2

Lecture 75 AXIL Master with only read Implementation P3

Lecture 76 AXIL Slave with only read Implementation P1

Lecture 77 AXIL Slave with only read Implementation P2

Lecture 78 Connecting Master and Slave

Lecture 79 Verifying Operation P1

Lecture 80 Verifying Operation P2

Lecture 81 Code

Lecture 82 Adding AXI protocol checker P1

Lecture 83 Adding AXI protocol checker P2

Lecture 84 Adding AXI protocol checker P3

Section 6: Single Beat without Pipeline : AXI Lite with FSM based approach

Lecture 85 Agenda

Lecture 86 Buidling FSM for Master

Lecture 87 Master I/O ports

Lecture 88 Master Implementation P1 : Write

Lecture 89 Master Implementation P2 : Write

Lecture 90 Master Implementation P3 : Read

Lecture 91 Verifying Operation of Master

Lecture 92 Design Code

Lecture 93 TB Code

Section 7: AXI Lite Used Case

Lecture 94 Building AXI lite GPIO IP P1 : Generating data from wdata and wstrb

Lecture 95 Building AXI lite GPIO IP P2 : Debouncing

Lecture 96 Building AXI lite GPIO IP P3: Write FSM

Lecture 97 Building AXI lite GPIO IP P4: read FSM

Lecture 98 Building AXI lite GPIO IP P4: Testing Operation

Lecture 99 Code

Section 8: AXI Full with hardcoded next address generation logic

Lecture 100 Typical AXI full transactions

Lecture 101 Write FSM

Lecture 102 Read FSM

Lecture 103 Implementing Write Channel

Lecture 104 Implementing Read Channel

Lecture 105 Code

Lecture 106 Implementing Slave Write Operation

Lecture 107 Slave Read Operation

Lecture 108 Code

Lecture 109 Connecting Master and Slave together and verifying design

Lecture 110 Code

Section 9: AXI Full with next address generation logic from Burst type

Lecture 111 Agenda

Lecture 112 Understanding Fixed mode

Lecture 113 Implementation of fixed mode during Write

Lecture 114 Understanding INCR mode

Lecture 115 Implementation of INCR mode during Write

Lecture 116 Understanding WRAP mode

Lecture 117 Implementation of WRAP mode during Write

Lecture 118 Burst modes implementation during Read Operation

Lecture 119 Implementing Master

Lecture 120 Code

Lecture 121 Implementing Slave Write

Lecture 122 Implementing Slave Read

Lecture 123 Code

Lecture 124 Connecting Master and Slave together

Lecture 125 Code

Lecture 126 TB Code

A VLSI engineer is interested in constructing Custom AXI peripheral in Verilog for SoC.