In August of 2006, an engineering VP from one of Altera’s customers approached Misha Burich, VP of Engineering at Altera, asking for help in reliably being able to predict the cost, schedule and quality of system designs reliant on FPGA designs. At this time, I was responsible for defining the design flow requirements for the Altera design software and was tasked with investigating this further. As I worked with the customer to understand what worked and what did not work reliably in their FPGA design process, I noted that this problem was not unique to this one customer. The characteristics of the problem are shared by many Corporations that implement designs in FPGAs. The Corporation has many design teams at different locations and the success of the FPGA projects vary between the teams. There is a wide range of design experience across the teams. There is no working process for sharing design blocks between engineering teams. As I analyzed the data that I had received from hundreds of customer visits in the past, I noticed that design reuse among engineering teams was a challenge. I also noticed that many of the design teams at the same Companies and even within the same design team used different design methodologies. Altera had recently solved this problem as part of its own FPGA design software and IP development process.

Field-Programmable Gate Arrays (FPGAs) have emerged as an attractive means of implementing logic circuits, providing instant manufacturing turnaround and negligible prototype costs. They hold the promise of replacing much of the VLSI market now held by mask-programmed gate arrays. FPGAs offer an affordable solution for customized VLSI, over a wide variety of applications, and have also opened up new possibilities in designing reconfigurable digital systems.

This book presents a new FPGA architecture known as tree-based FPGA architecture, due to its hierarchical nature. This type of architecture has been relatively unexplored despite their better performance and predictable routing behavior, as compared to mesh-based FPGA architectures. In this book, we explore and optimize the tree-based architecture and we evaluate it by comparing it to equivalent mesh-based FPGA architectures.

This book provides a broad introduction to Cognitive Radio, which attempts to mimic human cognition and reasoning applied to Software Defined Radio and reconfigurable radio over wireless networks. It provides readers with significant technical and practical insights into different aspects of Cognitive Radio, starting from a basic background, the principle behind the technology, the inter-related technologies and application to cellular and vehicular networks, the technical challenges, implementation and future trends. The discussion balances theoretical concepts and practical implementation. Wherever feasible, the different concepts explained are linked to application of the corresponding scheme in a particular wireless standard.

Embedded processors are the heart of embedded systems. Reconfigurable embedded processors comprise an extended instruction set that is implemented using a reconfigurable fabric (similar to a field-programmable gate array, FPGA). This book presents novel concepts, strategies, and implementations to increase the run-time adaptivity of reconfigurable embedded processors. Concepts and techniques are presented in an accessible, yet rigorous context. A complex, realistic H.264 video encoder application with a high demand for adaptivity is presented and used as an example for motivation throughout the book. A novel, run-time system is demonstrated to exploit the potential for adaptivity and particular approaches/algorithms are presented to implement it.